[PATCH v2 12/32] gpu: nova-core: mm: add BarMapping

From: Zhi Wang

Date: Mon Sep 14 2026 - 03:58:59 EST


vGPU communication buffers need CPU access to regions within their
VramBlocks. Add BarMapping to map these regions through BAR1, including
regions that start or end within a page.

Use BarUserAccess for the mapping and retain the backing region until
destruction. Restrict CPU accesses to the region's byte range.

Cc: Alistair Popple <apopple@xxxxxxxxxx>
Signed-off-by: Zhi Wang <zhiw@xxxxxxxxxx>
---
drivers/gpu/nova-core/mm/bar_user.rs | 105 +++++++++++++++++++++++++++
1 file changed, 105 insertions(+)

diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/mm/bar_user.rs
index 2e6d229b1a23..ef357fd516b7 100644
--- a/drivers/gpu/nova-core/mm/bar_user.rs
+++ b/drivers/gpu/nova-core/mm/bar_user.rs
@@ -18,6 +18,7 @@
MappedRange,
Vmm, //
},
+ vram::VramRegion,
GpuMm,
Pfn,
Vfn,
@@ -171,6 +172,110 @@ fn drop(&mut self) {
}
}

+/// A BAR1 mapping that retains its backing VRAM region.
+///
+/// Unmapping requires [`Self::destroy`]; dropping this object does not unmap it.
+#[must_use]
+pub(crate) struct BarMapping<'map, 'gpu> {
+ access: BarUserAccess<'map, 'gpu>,
+ region: VramRegion,
+ page_bias: usize,
+ logical_size: usize,
+}
+
+#[expect(dead_code)]
+impl<'map, 'gpu> BarMapping<'map, 'gpu> {
+ /// Maps the containing pages while restricting CPU access to the requested byte range.
+ pub(crate) fn new(
+ bar_user: &'map BarUser<'gpu>,
+ mm: &mut GpuMm<'_>,
+ region: VramRegion,
+ writable: bool,
+ ) -> Result<Self> {
+ let page_size: u64 = PAGE_SIZE.into_safe_cast();
+ let region_start = region.address();
+ let region_end = region_start.checked_add(region.size()).ok_or(EOVERFLOW)?;
+ let map_start = region_start - region_start % page_size;
+ let map_end =
+ region_end.checked_add(page_size - 1).ok_or(EOVERFLOW)? / page_size * page_size;
+ let map_size = map_end.checked_sub(map_start).ok_or(EINVAL)?;
+ let num_pages = usize::try_from(map_size / page_size).map_err(|_| EOVERFLOW)?;
+ if num_pages == 0 {
+ return Err(EINVAL);
+ }
+
+ let page_bias = usize::try_from(region_start - map_start).map_err(|_| EOVERFLOW)?;
+ let logical_size = usize::try_from(region.size()).map_err(|_| EOVERFLOW)?;
+ let mut pfns = KVec::with_capacity(num_pages, GFP_KERNEL)?;
+ for page in 0..num_pages {
+ let byte_offset = u64::try_from(page)
+ .map_err(|_| EOVERFLOW)?
+ .checked_mul(page_size)
+ .ok_or(EOVERFLOW)?;
+ let address = map_start.checked_add(byte_offset).ok_or(EOVERFLOW)?;
+ pfns.push(Pfn::from(VramAddress::from_raw(address)), GFP_KERNEL)?;
+ }
+
+ let access = bar_user.map(mm, &pfns, writable)?;
+
+ Ok(Self {
+ access,
+ region,
+ page_bias,
+ logical_size,
+ })
+ }
+
+ pub(crate) fn region(&self) -> &VramRegion {
+ &self.region
+ }
+
+ pub(crate) fn gpu_va_addr(&self) -> Result<u64> {
+ self.access
+ .base()
+ .into_raw()
+ .checked_add(u64::try_from(self.page_bias).map_err(|_| EOVERFLOW)?)
+ .ok_or(EOVERFLOW)
+ }
+
+ pub(crate) const fn size(&self) -> usize {
+ self.logical_size
+ }
+
+ fn access_offset(&self, offset: usize, width: usize) -> Result<usize> {
+ let logical_end = offset.checked_add(width).ok_or(EOVERFLOW)?;
+ if logical_end > self.logical_size {
+ return Err(EINVAL);
+ }
+
+ let access_offset = self.page_bias.checked_add(offset).ok_or(EOVERFLOW)?;
+ if !access_offset.is_multiple_of(width) {
+ return Err(EINVAL);
+ }
+
+ Ok(access_offset)
+ }
+
+ pub(crate) fn try_read32(&self, offset: usize) -> Result<u32> {
+ self.access
+ .try_read32(self.access_offset(offset, size_of::<u32>())?)
+ }
+
+ pub(crate) fn try_write32(&self, value: u32, offset: usize) -> Result {
+ self.access
+ .try_write32(value, self.access_offset(offset, size_of::<u32>())?)
+ }
+
+ pub(crate) fn try_write64(&self, value: u64, offset: usize) -> Result {
+ self.access
+ .try_write64(value, self.access_offset(offset, size_of::<u64>())?)
+ }
+
+ pub(crate) fn destroy(self, mm: &mut GpuMm<'_>) -> Result {
+ self.access.release(mm)
+ }
+}
+
/// Run MM subsystem self-tests during probe.
///
/// Tests page table infrastructure and `BAR1` MMIO access using the `BAR1`