[PATCH 2/2] clk: qcom: mmcc-sdm660: set num_parents on mdss_axi_clk

[Fabricio Akio via B4 Relay]

From: Fabricio Akio <fabricioakio@xxxxxxxxx>

mdss_axi_clk names axi_clk_src in parent_hws but leaves num_parents at
zero, so the array is never read and the branch registers as a root
clock -- no rate of its own, and no reference on its parent:

  axi_clk_src   en=0 rate=384000000
  mdss_axi_clk  en=1 rate=0

It is the only branch in this driver missing the field.

Fixes: 5db3ae8b33de ("clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver")
Signed-off-by: Fabricio Akio <fabricioakio@xxxxxxxxx>
---
 drivers/clk/qcom/mmcc-sdm660.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c
index 9f8b8e29fa0f..433f5954eb91 100644
--- a/drivers/clk/qcom/mmcc-sdm660.c
+++ b/drivers/clk/qcom/mmcc-sdm660.c
@@ -2064,6 +2064,7 @@ static struct clk_branch mdss_axi_clk = {
 		.hw.init = &(struct clk_init_data){
 			.name = "mdss_axi_clk",
 			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
+			.num_parents = 1,
 			.ops = &clk_branch2_ops,
 		},
 	},

-- 
2.55.0