Re: [PATCH v3 0/9] Add Aspeed AST2700 SDRAM EDAC support

[Borislav Petkov]

On Tue, Sep 29, 2026 at 03:26:42AM +0000, Ryan Chen wrote:
> > Subject: Re: [PATCH v3 0/9] Add Aspeed AST2700 SDRAM EDAC support
> > 
> > On Wed, Sep 16, 2026 at 01:30:37PM +0800, Ryan Chen wrote:
> > > Add ECC error reporting for the Aspeed AST2700 SoC to the existing
> > > aspeed_edac driver.
> > >
> > > The AST2700 memory controller keeps the same overall EDAC programming
> > > model as the earlier Aspeed BMC SoCs, but uses a different register
> > > layout, a split interrupt status/clear/mask scheme and DDR4/DDR5 memory.
> > > Rather than fork the driver, the existing code is first tidied and
> > > generalised, then the AST2700 is added as one more per-SoC variant.
> > >
> > > Patches 2-5 are bug fixes and cleanups to the existing driver.
> > 
> > You always put the bug fixes first in a set. So it should be 1-4 bugfixes, rest new
> > features.
> > 
> > --
> Thanks your review.

Not done yet but you can send a new version if you feel like it. For it, you
could also pick up Stefan's patch and merge it with your last one so that the
driver doesn't become orphan.

Also, think hard before you mark fixes as CC:stable because stable fixes
trigger a lot of work downstream: stable trees, distros etc. So consult:

Documentation/process/stable-kernel-rules.rst

before you do.

HTH and Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette