Re: [PATCH v4 7/7] riscv: dts: eswin: add watchdog support

[Pinkesh Vaghela]

Hi Samuel,

> -----Original Message-----
> From: Samuel Holland <samuel.holland@xxxxxxxxxx>
> Sent: Tuesday, September 29, 2026 6:42 PM
> To: Pinkesh Vaghela <pinkesh.vaghela@xxxxxxxxxxxxxx>
> Cc: Yulin Lu <luyulin@xxxxxxxxxxxxxxxxxx>; Darshan Prajapati
> <darshan.prajapati@xxxxxxxxxxxxxx>; Pritesh Patel
> <pritesh.patel@xxxxxxxxxxxxxx>; Rob Herring <robh@xxxxxxxxxx>; Krzysztof
> Kozlowski <krzk+dt@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>; Paul
> Walmsley <pjw@xxxxxxxxxx>; Palmer Dabbelt <palmer@xxxxxxxxxxx>; Albert
> Ou <aou@xxxxxxxxxxxxxxxxx>; Alexandre Ghiti <alex@xxxxxxxx>; Andi Shyti
> <andi.shyti@xxxxxxxxxx>; Mika Westerberg
> <mika.westerberg@xxxxxxxxxxxxxxx>; linux-i2c@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-
> riscv@xxxxxxxxxxxxxxxxxxx; Min Lin <linmin@xxxxxxxxxxxxxxxxxx>
> Subject: [External] Re: [PATCH v4 7/7] riscv: dts: eswin: add watchdog support
> 
> Hi Pinkesh,
> 
> On 2026-08-14 2:00 AM, Pinkesh Vaghela wrote:
> > From: Pritesh Patel <pritesh.patel@xxxxxxxxxxxxxx>
> >
> > Add watchdog node for ESWIN EIC7700 SoC and enable them for HiFive
> > Premier P550 board
> >
> > Signed-off-by: Pritesh Patel <pritesh.patel@xxxxxxxxxxxxxx>
> > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@xxxxxxxxxxxxxx>
> > ---
> >  .../dts/eswin/eic7700-hifive-premier-p550.dts | 16 ++++++++
> >  arch/riscv/boot/dts/eswin/eic7700.dtsi        | 40 +++++++++++++++++++
> >  2 files changed, 56 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > index 5dddcf13fd25..103c3dab184f 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > @@ -207,3 +207,19 @@ &uart2 {
> >       pinctrl-names = "default";
> >       pinctrl-0 = <&uart2_pins>;
> >  };
> > +
> > +&wdt0 {
> > +     status = "okay";
> > +};
> > +
> > +&wdt1 {
> > +     status = "okay";
> > +};
> > +
> > +&wdt2 {
> > +     status = "okay";
> > +};
> > +
> > +&wdt3 {
> > +     status = "okay";
> > +};
> 
> The watchdog timers have no dependency outside the SoC, so they can be
> enabled by default (omit the status property). There is no need to separately
> enable them for each board.

We will change this in next version.

Regards,
Pinkesh

> 
> Regards,
> Samuel
> 
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > index c13432d14504..f873e9eeb929 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > @@ -265,6 +265,46 @@ syscon: syscon@50440000 {
> >                       };
> >               };
> >
> > +             wdt0: watchdog@50800000 {
> > +                     compatible = "snps,dw-wdt";
> > +                     reg = <0x0 0x50800000 0x0 0x4000>;
> > +                     interrupts = <87>;
> > +                     clocks = <&clk EIC7700_CLK_GATE_LSP_WDT0_PCLK>;
> > +                     clock-names = "tclk";
> > +                     resets = <&reset EIC7700_RESET_WDT0>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             wdt1: watchdog@50804000 {
> > +                     compatible = "snps,dw-wdt";
> > +                     reg = <0x0 0x50804000 0x0 0x4000>;
> > +                     interrupts = <88>;
> > +                     clocks = <&clk EIC7700_CLK_GATE_LSP_WDT1_PCLK>;
> > +                     clock-names = "tclk";
> > +                     resets = <&reset EIC7700_RESET_WDT1>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             wdt2: watchdog@50808000 {
> > +                     compatible = "snps,dw-wdt";
> > +                     reg = <0x0 0x50808000 0x0 0x4000>;
> > +                     interrupts = <89>;
> > +                     clocks = <&clk EIC7700_CLK_GATE_LSP_WDT2_PCLK>;
> > +                     clock-names = "tclk";
> > +                     resets = <&reset EIC7700_RESET_WDT2>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             wdt3: watchdog@5080c000 {
> > +                     compatible = "snps,dw-wdt";
> > +                     reg = <0x0 0x5080c000 0x0 0x4000>;
> > +                     interrupts = <90>;
> > +                     clocks = <&clk EIC7700_CLK_GATE_LSP_WDT3_PCLK>;
> > +                     clock-names = "tclk";
> > +                     resets = <&reset EIC7700_RESET_WDT3>;
> > +                     status = "disabled";
> > +             };
> > +
> >               uart0: serial@50900000 {
> >                       compatible = "snps,dw-apb-uart";
> >                       reg = <0x0 0x50900000 0x0 0x10000>;