Re: [PATCH v6 0/8] riscv: optimize mode switch latency for Vector

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (for-next)
by Paul Walmsley <pjw@xxxxxxxxxx>:

On Fri, 18 Sep 2026 16:51:14 -0500 you wrote:
> This series provide several optimizations targeting system call latency
> regarding vector context management. Before the series, the kernel
> handled user's vector context in an conservative way, where registers
> were null out and VS is tracked as DIRTY. This introduce excess context
> saving and restoring when there is a context swicth.  Also, the kernel
> turned off Vector at the exception entry, making all in-kernel vector
> usecase take the serialization cost, which includes context switch and
> user copies. The cost is not easy to hide as vector code are usually sit
> right after enabling V.
> 
> [...]

Here is the summary with links:
  - [v6,1/8] riscv: do not read csr in vector context switch
    https://git.kernel.org/riscv/c/5fd018c630e2
  - [v6,2/8] riscv: vector: refactor context switch for kernel-mode vector
    https://git.kernel.org/riscv/c/4740b934ebe7
  - [v6,3/8] selftest: riscv: test vectorized user copy
    https://git.kernel.org/riscv/c/52318cf0fa6e
  - [v6,4/8] riscv: vector: refactor vector context operations
    https://git.kernel.org/riscv/c/1a5c75ee3d09
  - [v6,5/8] riscv: clarify vector state semantics on syscall and context switch
    https://git.kernel.org/riscv/c/cc12e55016ba
  - [v6,6/8] riscv: vector: adjust ptrace and signal behavior for INITIAL state
    https://git.kernel.org/riscv/c/0d4b43a7734d
  - [v6,7/8] selftests: riscv: Extend vector tests for sigreturn and ptrace
    https://git.kernel.org/riscv/c/6740ec489dd7
  - [v6,8/8] riscv: vector: optimize vstate operations
    (no matching commit)

You are awesome, thank you!
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