[PATCH v6 10/11] arm64: dts: qcom: ipq5210: Add SPI node definitions
From: Varadarajan Narayanan
Date: Thu Oct 08 2026 - 05:32:31 EST
Add SPI node definition for the QUP SPI blocks present in IPQ5210.
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
index 50ce79219fe2..23a2e27b70fa 100644
--- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
@@ -418,6 +418,17 @@ qupv3: geniqup@1ac0000 {
#address-cells = <2>;
#size-cells = <2>;
+ spi0: spi@1a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x1a80000 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_SE0_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&gcc GCC_QUPV3_WRAP_SE0_CLK>;
+ assigned-clock-rates = <50000000>;
+ status = "disabled";
+ };
+
uart1: serial@1a84000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x01a84000 0x0 0x4000>;
@@ -456,6 +467,17 @@ i2c1: i2c@1a8c000 {
status = "disabled";
};
+ spi1: spi@1a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01a90000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_SE4_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&gcc GCC_QUPV3_WRAP_SE4_CLK>;
+ assigned-clock-rates = <50000000>;
+ status = "disabled";
+ };
+
i2c2: i2c@1a94000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x01a94000 0x0 0x4000>;
--
2.34.1