[PATCH] clocksource/drivers/pistachio: fix leaked iomap on error paths

[Haotian Zhang]

pistachio_clksrc_of_init() maps the timer registers with of_iomap() and
stores the result in the static global pcs_gpt.base, but every error path
after the mapping (syscon lookup, regmap_update_bits, the two
of_clk_get_by_name() calls and both clk_prepare_enable() calls) returns
without calling iounmap(), leaking the mapping.

Route all these error paths through a common err_unmap label that calls
iounmap() and clears pcs_gpt.base.

Fixes: 84583983c319 ("CLOCKSOURCE: Add Pistachio clocksource-only driver")
Assisted-by: DeepSeek-V4.1-Flash
Signed-off-by: Haotian Zhang <vulab@xxxxxxxxxxx>
---
 drivers/clocksource/timer-pistachio.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/clocksource/timer-pistachio.c b/drivers/clocksource/timer-pistachio.c
index 57b2197a0b67..e94faed5009f 100644
--- a/drivers/clocksource/timer-pistachio.c
+++ b/drivers/clocksource/timer-pistachio.c
@@ -163,38 +163,41 @@ static int __init pistachio_clksrc_of_init(struct device_node *node)
 	if (IS_ERR(periph_regs)) {
 		pr_err("cannot get peripheral regmap (%ld)\n",
 		       PTR_ERR(periph_regs));
-		return PTR_ERR(periph_regs);
+		ret = PTR_ERR(periph_regs);
+		goto err_unmap;
 	}
 
 	/* Switch to using the fast counter clock */
 	ret = regmap_update_bits(periph_regs, PERIP_TIMER_CONTROL,
 				 0xf, 0x0);
 	if (ret)
-		return ret;
+		goto err_unmap;
 
 	sys_clk = of_clk_get_by_name(node, "sys");
 	if (IS_ERR(sys_clk)) {
 		pr_err("clock get failed (%ld)\n", PTR_ERR(sys_clk));
-		return PTR_ERR(sys_clk);
+		ret = PTR_ERR(sys_clk);
+		goto err_unmap;
 	}
 
 	fast_clk = of_clk_get_by_name(node, "fast");
 	if (IS_ERR(fast_clk)) {
 		pr_err("clock get failed (%lu)\n", PTR_ERR(fast_clk));
-		return PTR_ERR(fast_clk);
+		ret = PTR_ERR(fast_clk);
+		goto err_unmap;
 	}
 
 	ret = clk_prepare_enable(sys_clk);
 	if (ret < 0) {
 		pr_err("failed to enable clock (%d)\n", ret);
-		return ret;
+		goto err_unmap;
 	}
 
 	ret = clk_prepare_enable(fast_clk);
 	if (ret < 0) {
 		pr_err("failed to enable clock (%d)\n", ret);
 		clk_disable_unprepare(sys_clk);
-		return ret;
+		goto err_unmap;
 	}
 
 	rate = clk_get_rate(fast_clk);
@@ -211,6 +214,11 @@ static int __init pistachio_clksrc_of_init(struct device_node *node)
 	raw_spin_lock_init(&pcs_gpt.lock);
 	sched_clock_register(pistachio_read_sched_clock, 32, rate);
 	return clocksource_register_hz(&pcs_gpt.cs, rate);
+
+err_unmap:
+	iounmap(pcs_gpt.base);
+	pcs_gpt.base = NULL;
+	return ret;
 }
 TIMER_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
 		       pistachio_clksrc_of_init);
-- 
2.25.1