[PATCH 1/3] ARM: dts: imx6qdl: Move board Root Port children under &pcie_port0

From: Sherry Sun (OSS)

Date: Wed Oct 21 2026 - 05:09:53 EST


From: Sherry Sun <sherry.sun@xxxxxxx>

Commit 9dc39532172c ("ARM: dts: imx6qdl: Add Root Port node and PERST
property") added a Root Port node pcie@0 to the SoC level host bridge.
However, some boards already described the Root Port with a different
node name:
imx6qdl-zii-rdu2.dtsi: host@0
imx6q-bx50v3.dtsi: root@0,0 (labeled pci_root, extended by the
b450v3/b650v3/b850v3 board files)

Both nodes now share devfn 0 under the same host bridge.
of_pci_find_child_device() returns the first match, which is the SoC
pcie@0 node, so the board level Root Port node and all of its children
become stale.

Fix this by moving the children of the board level Root Port nodes
under &pcie_port0 and dropping the duplicated board level Root Port
nodes.

The moved nodes are now located on the secondary bus of the Root Port
(bus 1), so update their reg bus number and unit addresses accordingly
to keep dtc pci_device_reg/pci_device_bus_num checks happy. Only the
devfn is used to match the PCI device to its DT node, so this does not
change the matching.

Fixes: 9dc39532172c ("ARM: dts: imx6qdl: Add Root Port node and PERST property")
Reported-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
Closes: https://lore.kernel.org/all/171421fb-d0a6-4e3f-b2dc-226e9c548972@xxxxxxxxxxxxxx/
Signed-off-by: Sherry Sun <sherry.sun@xxxxxxx>
---
arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts | 4 ++--
arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts | 4 ++--
arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts | 4 ++--
arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi | 11 -----------
arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi | 13 ++++---------
5 files changed, 10 insertions(+), 26 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
index 7326b8ad08cb..efddf3ce0df2 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
@@ -104,9 +104,9 @@ P07-hog {
};
};

-&pci_root {
+&pcie_port0 {
/* Intel Corporation I210 Gigabit Network Connection */
- switch_nic: ethernet@3,0 {
+ switch_nic: ethernet@0,0 {
compatible = "pci8086,1533";
reg = <0x00010000 0 0 0 0>;
};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts
index 9a43935be11c..d60a8b8f1f6f 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts
@@ -103,9 +103,9 @@ &usbphy1 {
fsl,tx-d-cal = <100>;
};

-&pci_root {
+&pcie_port0 {
/* Intel Corporation I210 Gigabit Network Connection */
- switch_nic: ethernet@3,0 {
+ switch_nic: ethernet@0,0 {
compatible = "pci8086,1533";
reg = <0x00010000 0 0 0 0>;
};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
index d00236a07dc4..922a257d44b4 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
@@ -231,9 +231,9 @@ P11-hog {
};
};

-&pci_root {
+&pcie_port0 {
/* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */
- bridge@1,0 {
+ bridge@0,0 {
compatible = "pci10b5,8605";
reg = <0x00010000 0 0 0 0>;

diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi
index 2c8d2ab8cda1..2002002052d2 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi
@@ -391,17 +391,6 @@ wlcore: wlcore@2 {
};
};

-&pcie {
- /* Synopsys, Inc. Device */
- pci_root: root@0,0 {
- compatible = "pci16c3,abcd";
- reg = <0x00000000 0 0 0 0>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- };
-};
-
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi
index 601733c3c2a9..b8006e364732 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi
@@ -653,16 +653,11 @@ &pcie {
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
status = "okay";
+};

- host@0 {
- reg = <0 0 0 0 0>;
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- i210: i210@0 {
- reg = <0 0 0 0 0>;
- };
+&pcie_port0 {
+ i210: i210@0 {
+ reg = <0x10000 0 0 0 0>;
};
};


--
2.50.1