[PATCH v1] arm64: dts: imx91: add U-Boot bootph properties
From: alice . guo
Date: Fri Oct 30 2026 - 10:49:43 EST
From: Alice Guo <alice.guo@xxxxxxx>
Add bootph-pre-ram, bootph-some-ram and bootph-all properties needed by
U-Boot for early boot DT processing.
Place the properties in the Linux DT sources so they can be consumed
directly by U-Boot when generating its device tree. SoC-level nodes are
updated in imx91_93_common.dtsi, while board-specific nodes are updated
in imx91-9x9-qsb.dts.
The properties match the current requirements of the i.MX91 9x9 QSB
platform and include the clocks, bus, GPIO, mailbox, USDHC, LPI2C, UART,
PMIC and related pinctrl nodes used during early boot.
Signed-off-by: Alice Guo <alice.guo@xxxxxxx>
---
.../boot/dts/freescale/imx91-9x9-qsb.dts | 21 ++++++++++++++++++
.../boot/dts/freescale/imx91_93_common.dtsi | 22 +++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts
index b7f0e39b867a..fbb7de8c0a12 100644
--- a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts
+++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts
@@ -172,6 +172,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
regulator-min-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
+ bootph-pre-ram;
};
reserved-memory {
@@ -257,6 +258,7 @@ pinctrl_lpi2c1: lpi2c1grp {
MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
+ bootph-pre-ram;
};
pinctrl_lpi2c2: lpi2c2grp {
@@ -264,6 +266,7 @@ pinctrl_lpi2c2: lpi2c2grp {
MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
+ bootph-pre-ram;
};
pinctrl_pcal6524: pcal6524grp {
@@ -284,6 +287,7 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
>;
+ bootph-pre-ram;
};
pinctrl_sai1: sai1grp {
@@ -300,6 +304,8 @@ pinctrl_uart1: uart1grp {
MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
+ bootph-pre-ram;
+ bootph-some-ram;
};
pinctrl_usdhc1: usdhc1grp {
@@ -316,6 +322,7 @@ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
+ bootph-pre-ram;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
@@ -332,6 +339,7 @@ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
+ bootph-pre-ram;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
@@ -348,12 +356,14 @@ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
+ bootph-pre-ram;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
>;
+ bootph-pre-ram;
};
pinctrl_usdhc2: usdhc2grp {
@@ -366,6 +376,7 @@ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
+ bootph-pre-ram;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -378,6 +389,7 @@ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
+ bootph-pre-ram;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -390,6 +402,7 @@ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
+ bootph-pre-ram;
};
pinctrl_wdog: wdoggrp {
@@ -404,6 +417,7 @@ &lpi2c1 {
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-names = "default";
status = "okay";
+ bootph-pre-ram;
p3t1085: temperature-sensor@48 {
compatible = "nxp,p3t1085";
@@ -455,6 +469,7 @@ &lpi2c2 {
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-names = "default";
status = "okay";
+ bootph-pre-ram;
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
@@ -474,8 +489,10 @@ pmic@32 {
reg = <0x32>;
interrupt-parent = <&pcal6524>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ bootph-pre-ram;
regulators {
+ bootph-pre-ram;
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-always-on;
@@ -540,6 +557,8 @@ &lpuart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
+ bootph-pre-ram;
+ bootph-some-ram;
};
&micfil {
@@ -623,6 +642,7 @@ &usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
fsl,tuning-step = <1>;
status = "okay";
+ bootph-pre-ram;
};
&usdhc2 {
@@ -637,6 +657,7 @@ &usdhc2 {
vmmc-supply = <®_usdhc2_vmmc>;
fsl,tuning-step = <1>;
status = "okay";
+ bootph-pre-ram;
};
&wdog3 {
diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
index a68ffd04ee08..65e66309bc1d 100644
--- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
@@ -51,6 +51,7 @@ osc_32k: clock-osc-32k {
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "osc_32k";
+ bootph-all;
};
osc_24m: clock-osc-24m {
@@ -58,6 +59,7 @@ osc_24m: clock-osc-24m {
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc_24m";
+ bootph-all;
};
clk_ext1: clock-ext1 {
@@ -65,6 +67,7 @@ clk_ext1: clock-ext1 {
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext1";
+ bootph-all;
};
pmu {
@@ -136,6 +139,7 @@ soc@0 {
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x80000000>,
<0x28000000 0x0 0x28000000 0x10000000>;
+ bootph-all;
aips1: bus@44000000 {
compatible = "fsl,aips-bus", "simple-bus";
@@ -143,6 +147,7 @@ aips1: bus@44000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ bootph-all;
edma1: dma-controller@44000000 {
compatible = "fsl,imx93-edma3";
@@ -357,6 +362,8 @@ iomuxc: pinctrl@443c0000 {
compatible = "fsl,imx93-iomuxc";
reg = <0x443c0000 0x10000>;
status = "okay";
+ bootph-pre-ram;
+ bootph-some-ram;
};
bbnsm: bbnsm@44440000 {
@@ -384,6 +391,7 @@ clk: clock-controller@44450000 {
assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <393216000>;
status = "okay";
+ bootph-all;
};
src: system-controller@44460000 {
@@ -444,6 +452,8 @@ aips2: bus@42000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ bootph-pre-ram;
+ bootph-some-ram;
edma2: dma-controller@42000000 {
compatible = "fsl,imx93-edma4";
@@ -919,6 +929,8 @@ aips3: bus@42800000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ bootph-pre-ram;
+ bootph-some-ram;
usdhc1: mmc@42850000 {
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
@@ -1039,6 +1051,8 @@ gpio2: gpio@43810000 {
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 4 30>;
ngpios = <30>;
+ bootph-pre-ram;
+ bootph-some-ram;
};
gpio3: gpio@43820000 {
@@ -1056,6 +1070,8 @@ gpio3: gpio@43820000 {
gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
<&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
ngpios = <32>;
+ bootph-pre-ram;
+ bootph-some-ram;
};
gpio4: gpio@43830000 {
@@ -1072,6 +1088,8 @@ gpio4: gpio@43830000 {
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
ngpios = <30>;
+ bootph-pre-ram;
+ bootph-some-ram;
};
gpio1: gpio@47400000 {
@@ -1088,6 +1106,8 @@ gpio1: gpio@47400000 {
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 92 16>;
ngpios = <16>;
+ bootph-pre-ram;
+ bootph-some-ram;
};
ocotp: efuse@47510000 {
@@ -1113,6 +1133,8 @@ s4muap: mailbox@47520000 {
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
#mbox-cells = <2>;
+ bootph-pre-ram;
+ bootph-some-ram;
};
media_blk_ctrl: system-controller@4ac10000 {
--
2.34.1