[PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support
From: Shawn Guo
Date: Sun Nov 01 2026 - 03:05:39 EST
From: Mohd Ayaan Anwar <mohd.anwar@xxxxxxxxxxxxxxxx>
Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and
SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams
and DMA queues.
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@xxxxxxxxxxxxxxxx>
Signed-off-by: Shawn Guo <shengchao.guo@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 124 +++++++++
arch/arm64/boot/dts/qcom/nord.dtsi | 282 ++++++++++++++++++++
2 files changed, 406 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index 6dc4c871f41e..72094c84e346 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -42,6 +42,60 @@ &crypto {
status = "okay";
};
+ðernet0 {
+ clocks = <&segcc SE_GCC_EMAC0_AXI_CLK>,
+ <&segcc SE_GCC_EMAC0_CNOC_APB_CLK>,
+ <&segcc SE_GCC_EMAC0_PTP_CLK>,
+ <&segcc SE_GCC_EMAC0_PHY_AUX_CLK>,
+ <&segcc SE_GCC_EEE_EMAC0_CLK>;
+ clock-names = "stmmaceth",
+ "pclk",
+ "ptp_ref",
+ "phyaux",
+ "eee";
+
+ resets = <&segcc SE_GCC_EMAC0_BCR>;
+
+ power-domains = <&segcc SE_GCC_EMAC0_GDSC>;
+
+ interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_PS_ETH_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc_tile MASTER_EMAC_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-mac",
+ "mac-mem";
+
+ phys = <&serdes0>;
+ phy-names = "serdes";
+};
+
+ðernet1 {
+ clocks = <&segcc SE_GCC_EMAC1_AXI_CLK>,
+ <&segcc SE_GCC_EMAC1_CNOC_APB_CLK>,
+ <&segcc SE_GCC_EMAC1_PTP_CLK>,
+ <&segcc SE_GCC_EMAC1_PHY_AUX_CLK>,
+ <&segcc SE_GCC_EEE_EMAC1_CLK>;
+ clock-names = "stmmaceth",
+ "pclk",
+ "ptp_ref",
+ "phyaux",
+ "eee";
+
+ resets = <&segcc SE_GCC_EMAC1_BCR>;
+
+ power-domains = <&segcc SE_GCC_EMAC1_GDSC>;
+
+ interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_PS_ETH_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc_tile MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-mac",
+ "mac-mem";
+
+ phys = <&serdes1>;
+ phy-names = "serdes";
+};
+
&i2c0 {
clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
@@ -857,6 +911,30 @@ hpass_ag_noc: interconnect@5fc0000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ serdes0: phy@88f8000 {
+ compatible = "qcom,nord-dwmac-sgmii-phy";
+ reg = <0x0 0x088f8000 0x0 0x4000>;
+
+ clocks = <&tcsrcc TCSR_UX_SGMII_0_CLKREF_EN>;
+ clock-names = "sgmi_ref";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ serdes1: phy@88fc000 {
+ compatible = "qcom,nord-dwmac-sgmii-phy";
+ reg = <0x0 0x088fc000 0x0 0x4000>;
+
+ clocks = <&tcsrcc TCSR_UX_SGMII_1_CLKREF_EN>;
+ clock-names = "sgmi_ref";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
negcc: clock-controller@8900000 {
compatible = "qcom,nord-negcc";
reg = <0x0 0x08900000 0x0 0xf4200>;
@@ -1106,6 +1184,38 @@ nsp_data_noc_3: interconnect@1fe00000 {
};
&tlmm {
+ ethernet0_default: ethernet0-default-state {
+ mdc-pins {
+ pins = "gpio47";
+ function = "emac0_mdc";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio48";
+ function = "emac0_mdio";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ ethernet1_default: ethernet1-default-state {
+ mdc-pins {
+ pins = "gpio49";
+ function = "emac1_mdc";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio50";
+ function = "emac1_mdio";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
qup_i2c0_default: qup-i2c0-default-state {
pins = "gpio111", "gpio112";
function = "qup0_se0";
@@ -1989,3 +2099,17 @@ opp-403000000 {
};
};
};
+
+&xpcs0 {
+ clocks = <&segcc SE_GCC_EMAC0_CNOC_APB_CLK>;
+ clock-names = "csr";
+
+ power-domains = <&segcc SE_GCC_EMAC0_GDSC>;
+};
+
+&xpcs1 {
+ clocks = <&segcc SE_GCC_EMAC1_CNOC_APB_CLK>;
+ clock-names = "csr";
+
+ power-domains = <&segcc SE_GCC_EMAC1_GDSC>;
+};
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index dfbbaf94a7ae..586fedd2580d 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -1593,6 +1593,288 @@ rng: rng@10c3000 {
reg = <0x0 0x010c3000 0x0 0x1000>;
};
+ ethernet0: ethernet@1a00000 {
+ compatible = "qcom,nord-ethqos";
+
+ reg = <0x0 0x01a00000 0x0 0x14000>,
+ <0x0 0x01a7f000 0x0 0x1000>;
+ reg-names = "stmmaceth",
+ "rgmii";
+
+ interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "eth_lpi";
+
+ iommus = <&apps_smmu_2 0x1201 0x2>,
+ <&apps_smmu_2 0x1202 0x0>,
+ <&apps_smmu_2 0x1203 0x2>,
+ <&apps_smmu_2 0x1204 0x0>,
+ <&apps_smmu_2 0x1205 0x2>,
+ <&apps_smmu_2 0x1206 0x0>,
+ <&apps_smmu_2 0x1207 0x2>,
+ <&apps_smmu_2 0x1208 0x0>,
+ <&apps_smmu_2 0x1209 0x0>,
+ <&apps_smmu_2 0x120a 0x0>;
+
+ pcs-handle = <&xpcs0>;
+
+ dma-coherent;
+
+ rx-fifo-depth = <98304>;
+ tx-fifo-depth = <98304>;
+
+ snps,tso;
+ snps,pbl = <16>;
+ snps,axi-config = <&emac0_axi_setup>;
+ snps,mtl-rx-config = <&emac0_mtl_rx>;
+ snps,mtl-tx-config = <&emac0_mtl_tx>;
+
+ status = "disabled";
+
+ emac0_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <16>;
+ snps,rd_osr_lmt = <16>;
+ snps,blen = <0 0 0 0 16 0 0>;
+ };
+
+ emac0_mtl_rx: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ snps,route-ptp;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ snps,route-avcp;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ snps,priority = <0xc>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x7>;
+ };
+ };
+
+ emac0_mtl_tx: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ xpcs0: xpcs@1a14000 {
+ compatible = "qcom,nord-dw-xpcs";
+
+ reg = <0x0 0x01a14000 0x0 0x5100>;
+ reg-names = "direct";
+ reg-io-width = <4>;
+
+ status = "disabled";
+ };
+
+ ethernet1: ethernet@1a80000 {
+ compatible = "qcom,nord-ethqos";
+
+ reg = <0x0 0x01a80000 0x0 0x14000>,
+ <0x0 0x01aff000 0x0 0x1000>;
+ reg-names = "stmmaceth",
+ "rgmii";
+
+ interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "eth_lpi";
+
+ iommus = <&apps_smmu_2 0x11c1 0x8>,
+ <&apps_smmu_2 0x11c2 0x1>,
+ <&apps_smmu_2 0x11c3 0x1>,
+ <&apps_smmu_2 0x11c4 0x3>,
+ <&apps_smmu_2 0x11c5 0x3>,
+ <&apps_smmu_2 0x11c6 0x3>,
+ <&apps_smmu_2 0x11c7 0x3>,
+ <&apps_smmu_2 0x11c8 0x2>,
+ <&apps_smmu_2 0x11c9 0x8>,
+ <&apps_smmu_2 0x11ca 0x2>;
+
+ pcs-handle = <&xpcs1>;
+
+ dma-coherent;
+
+ rx-fifo-depth = <98304>;
+ tx-fifo-depth = <98304>;
+
+ snps,tso;
+ snps,pbl = <16>;
+ snps,axi-config = <&emac1_axi_setup>;
+ snps,mtl-rx-config = <&emac1_mtl_rx>;
+ snps,mtl-tx-config = <&emac1_mtl_tx>;
+
+ status = "disabled";
+
+ emac1_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <16>;
+ snps,rd_osr_lmt = <16>;
+ snps,blen = <0 0 0 0 16 0 0>;
+ };
+
+ emac1_mtl_rx: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ snps,route-ptp;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ snps,route-avcp;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ snps,priority = <0xc>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x7>;
+ };
+ };
+
+ emac1_mtl_tx: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ xpcs1: xpcs@1a94000 {
+ compatible = "qcom,nord-dw-xpcs";
+
+ reg = <0x0 0x01a94000 0x0 0x5100>;
+ reg-names = "direct";
+ reg-io-width = <4>;
+
+ status = "disabled";
+ };
+
ufs_mem_hc: ufshc@1d44000 {
compatible = "qcom,nord-ufshc",
"qcom,ufshc",
--
2.43.0