Re: (subset) [PATCH 0/3] Tegra114: Fix CPU DFLL voltages

[Brian Masney]

On Thu, 29 Oct 2026 10:32:58 +0100, Patrick Fischer wrote:
> Tegra114: Fix CPU DFLL voltages
> 
> Since the Tegra114 CPU DFLL got its CVB tables in v6.18, it computes
> the CPU OPP voltages from tegra_sku_info.cpu_speedo_value and the step
> of the vdd_cpu regulator. On a Tegra Note 7 (Tegra114, TPS65913) every
> CPU OPP from 306 MHz to 1810.5 MHz ends up at 1000 mV, and the DFLL
> never changes vdd_cpu: it stays at the 1.10 V left by the bootloader,
> and the CPU runs at about 1.34 GHz whatever cpufreq requests. Three
> bugs cause this:
> 
> [...]

Applied, thanks!

[3/3] clk: tegra: dfll: Get the voltage step of range-based regulators
      https://git.kernel.org/clk/linux/c/fc1f8f0ceb3b

Best regards,
-- 
Brian Masney <masneyb@xxxxxxxxxx>