Re: [PATCH 4/4] clk: siflower: Add SF19A2890 peripheral clock and reset manager driver

[Chuanhong Guo]

Hi!

On Wed, Nov 4, 2026 at 5:25 PM Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> wrote:
> [...]
> > +
> > +static const u32 sf19a2890_gmac_resets[] = { GENMASK(1, 0) };
>
> Are these two bits separate resets? Are they individually controllable?
> Why are they bundled into a single reset_control like this? The commit
> message doesn't explain.

These are reset lines from the same IP block for different clock domains.
They have to be asserted together even though there are two lines.
See nUARTRST in [1] for an example of PL011.
The gmac lines are for two sides of the same async axi bridge.
Asserting them separately causes a bus lockup.

[1] https://support.arm.com/documentation/ddi0183/g/signal-descriptions/on-chip-signals
-- 
Regards,
Chuanhong Guo