Re: [PATCH 4/4] clk: siflower: Add SF19A2890 peripheral clock and reset manager driver

[Joseph Telaak]

> These are reset lines from the same IP block for different clock domains.
> They have to be asserted together even though there are two lines.
> [...]
> The gmac lines are for two sides of the same async axi bridge.
> Asserting them separately causes a bus lockup.

Thanks. v2 will explain it in the commit
message and keep one reset per group.