Re: [PATCH] pinctrl: amd: Clear interrupt enable on spurious IRQ and skip unhandled EOI

[Linus Walleij]

On Fri, Oct 30, 2026 at 8:50 PM Munique Feitoza
<muniquefeitoz4@xxxxxxxxx> wrote:

> When do_amd_gpio_irq_handler() detects a spurious interrupt on a pin
> that is not configured as an IRQ line (!gpiochip_line_is_irq()), it
> currently only clears BIT(INTERRUPT_MASK_OFF) while leaving
> BIT(INTERRUPT_ENABLE_OFF) set. Unlike amd_gpio_irq_disable(), leaving
> INTERRUPT_ENABLE_OFF enabled allows the pin status bit to keep
> re-asserting in WAKE_INT_STATUS_REG0/1. Clear both INTERRUPT_MASK_OFF
> and INTERRUPT_ENABLE_OFF when disabling a spurious GPIO IRQ on both
> main and RGPIO banks.
>
> Additionally, if no GPIO interrupt was handled (ret == false), return
> early before acquiring gpio_dev->lock and writing EOI_MASK to
> WAKE_INT_MASTER_REG. This avoids unnecessary MMIO accesses and spinlock
> contention when the IRQ line is shared or asserted by an unhandled
> spurious interrupt storm.
>
> Signed-off-by: Munique Feitoza <muniquefeitoz4@xxxxxxxxx>

Sashiko comments aside, we really need to put Mario on CC for
AMD patches, Mario what about adding yourself to this MAINTAINERS
entry:

PIN CONTROLLER - AMD
M:      Basavaraj Natikar <Basavaraj.Natikar@xxxxxxx>
M:      Shyam Sundar S K <Shyam-sundar.S-k@xxxxxxx>
S:      Maintained
F:      drivers/pinctrl/pinctrl-amd.c


Yours,
Linus Walleij