Re: [PATCH] pinctrl: amd: Clear interrupt enable on spurious IRQ and skip unhandled EOI

[Munique Feitoza]

Hi Mario,

This is a real issue observed on my desktop system during boot:

CPU: AMD Ryzen 5 5500
Motherboard: HA0QING A520 (BIOS 5.17)

During boot, the system experiences an interrupt storm on the AMD GPIO
controller (IRQ 7), eventually triggering irq 7: nobody cared and
leading the kernel to disable the IRQ line entirely:

´´´
irq 7: nobody cared (try booting with the "irqpoll" option)
CPU: 5 UID: 0 PID: 0 Comm: swapper/5 Not tainted 7.2.14-arch1-1 #1 PREEMPT(full)
Hardware name: HA0QING A520/A520, BIOS 5.17 04/02/2026
Call Trace:
 <IRQ>
 dump_stack_lvl+0x5d/0x80
 __report_bad_irq+0x35/0xaa
 note_interrupt.cold+0x1a/0x58
 handle_irq_event+0x72/0x90
 handle_fasteoi_irq+0xb6/0x1f0
 ...
handlers:
[<00000000d546c9c3>] amd_gpio_irq_handler
Disabling IRQ #7
´´´

Checking /proc/interrupts shows IRQ 7 (pinctrl_amd) accumulating
around 200,000 unhandled interrupts on core 5 before being disabled.

When looking into do_amd_gpio_irq_handler(), pins that trigger an
interrupt but are not registered as IRQ lines
(!gpiochip_line_is_irq()) only have BIT(INTERRUPT_MASK_OFF) cleared
while BIT(INTERRUPT_ENABLE_OFF) remains set. Clearing both bits stops
the spurious interrupt status from re-asserting.

Best regards,
Munique Feitoza

On Thu, Nov 5, 2026 at 5:18 AM Linus Walleij <linusw@xxxxxxxxxx> wrote:
>
> On Fri, Oct 30, 2026 at 8:50 PM Munique Feitoza
> <muniquefeitoz4@xxxxxxxxx> wrote:
>
> > When do_amd_gpio_irq_handler() detects a spurious interrupt on a pin
> > that is not configured as an IRQ line (!gpiochip_line_is_irq()), it
> > currently only clears BIT(INTERRUPT_MASK_OFF) while leaving
> > BIT(INTERRUPT_ENABLE_OFF) set. Unlike amd_gpio_irq_disable(), leaving
> > INTERRUPT_ENABLE_OFF enabled allows the pin status bit to keep
> > re-asserting in WAKE_INT_STATUS_REG0/1. Clear both INTERRUPT_MASK_OFF
> > and INTERRUPT_ENABLE_OFF when disabling a spurious GPIO IRQ on both
> > main and RGPIO banks.
> >
> > Additionally, if no GPIO interrupt was handled (ret == false), return
> > early before acquiring gpio_dev->lock and writing EOI_MASK to
> > WAKE_INT_MASTER_REG. This avoids unnecessary MMIO accesses and spinlock
> > contention when the IRQ line is shared or asserted by an unhandled
> > spurious interrupt storm.
> >
> > Signed-off-by: Munique Feitoza <muniquefeitoz4@xxxxxxxxx>
>
> Sashiko comments aside, we really need to put Mario on CC for
> AMD patches, Mario what about adding yourself to this MAINTAINERS
> entry:
>
> PIN CONTROLLER - AMD
> M:      Basavaraj Natikar <Basavaraj.Natikar@xxxxxxx>
> M:      Shyam Sundar S K <Shyam-sundar.S-k@xxxxxxx>
> S:      Maintained
> F:      drivers/pinctrl/pinctrl-amd.c
>
>
> Yours,
> Linus Walleij