Re: [PATCH v2] pinctrl: amd: Clear interrupt enable bit on spurious GPIO IRQ

[Munique Feitoza]

Hi Linus, Mario,

Adding Mario to CC as requested for v2.

Mario, could you please take a look at the v2 patch?

Best regards,
Munique


On Thu, Nov 5, 2026 at 5:19 AM Linus Walleij <linusw@xxxxxxxxxx> wrote:
>
> On Fri, Oct 30, 2026 at 9:08 PM Munique Feitoza
> <muniquefeitoz4@xxxxxxxxx> wrote:
>
> > When do_amd_gpio_irq_handler() detects a spurious interrupt on a pin
> > that is not configured as an IRQ line (!gpiochip_line_is_irq()), it
> > currently only clears BIT(INTERRUPT_MASK_OFF) while leaving
> > BIT(INTERRUPT_ENABLE_OFF) set. Unlike amd_gpio_irq_disable(), leaving
> > INTERRUPT_ENABLE_OFF enabled allows the pin interrupt status bit to
> > keep asserting in WAKE_INT_STATUS_REG0/1.
> >
> > Clear both INTERRUPT_MASK_OFF and INTERRUPT_ENABLE_OFF when disabling
> > a spurious GPIO IRQ on both the main and RGPIO banks.
> >
> > Signed-off-by: Munique Feitoza <muniquefeitoz4@xxxxxxxxx>
> > ---
> > Changes in v2:
> > - Drop the early return on !ret before writing EOI_MASK to
> >   WAKE_INT_MASTER_REG so that spurious GPIO interrupts disabled in the
> >   !gpiochip_line_is_irq() path still receive an EOI signal on the
> >   controller.
>
> Loop in Mario on v2
>
> Yours,
> Linus Walleij