Re: [PATCH v2] pinctrl: amd: Clear interrupt enable bit on spurious GPIO IRQ

[Mario Limonciello]

> > > When do_amd_gpio_irq_handler() detects a spurious interrupt on a pin
> > > that is not configured as an IRQ line (!gpiochip_line_is_irq()), it
> > > currently only clears BIT(INTERRUPT_MASK_OFF) while leaving
> > > BIT(INTERRUPT_ENABLE_OFF) set. Unlike amd_gpio_irq_disable(), leaving
> > > INTERRUPT_ENABLE_OFF enabled allows the pin interrupt status bit to
> > > keep asserting in WAKE_INT_STATUS_REG0/1.
> > >
> > > Clear both INTERRUPT_MASK_OFF and INTERRUPT_ENABLE_OFF when disabling
> > > a spurious GPIO IRQ on both the main and RGPIO banks.
> > >
> > > Signed-off-by: Munique Feitoza <muniquefeitoz4@xxxxxxxxx>
I'd like to understand more about this situation that lead you to this 
patch before we decide which way to go on the patch.

Was this just analyzing the code and looking for a code flow problem? 
Or do you have a real problem on a real system and came up with this to 
fix it?