Re: [PATCH] arm64: dts: qcom: glymur-qcb: Add PCIe3a support

[Sivansh Gupta]

On 2026-11-05 01:07 -0800, Qiang Yu wrote:
> Add support for the PCIe3a x8 slot on the Glymur QCB board, wiring up its
> regulators, pinctrl states, and PHY/port power supplies.
> 
> Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/glymur-qcb.dts | 117 ++++++++++++++++++++++++++++++++
>  1 file changed, 117 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/glymur-qcb.dts b/arch/arm64/boot/dts/qcom/glymur-qcb.dts
> index 17d8ff3aed23..741a24454e80 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-qcb.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-qcb.dts
> @@ -78,6 +78,48 @@ vreg_nvme: regulator-nvme {
>  		regulator-boot-on;
>  	};
>  
> +	vreg_pcie_12v: regulator-pcie-12v {
> +		compatible = "regulator-fixed";
> +
> +		regulator-name = "VREG_PCIE_12V";
> +		regulator-min-microvolt = <12000000>;
> +		regulator-max-microvolt = <12000000>;
> +
> +		gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +
> +		pinctrl-0 = <&pcie_x8_12v>;
> +		pinctrl-names = "default";
> +	};
> +
> +	vreg_pcie_3v3: regulator-pcie-3v3 {
> +		compatible = "regulator-fixed";
> +
> +		regulator-name = "VREG_PCIE_3P3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +
> +		gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +
> +		pinctrl-0 = <&pm_main_3p3_en>;
> +		pinctrl-names = "default";
> +	};
> +
> +	vreg_pcie_3v3_aux: regulator-pcie-3v3-aux {
> +		compatible = "regulator-fixed";
> +
> +		regulator-name = "VREG_PCIE_3P3_AUX";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +
> +		gpio = <&tlmm 136 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +
> +		pinctrl-0 = <&pm_aux_3p3_en>;
> +		pinctrl-names = "default";
> +	};
> +
>  	vreg_wcn_0p95: regulator-wcn-0p95 {
>  		compatible = "regulator-fixed";
>  
> @@ -438,6 +480,31 @@ embedded-controller@76 {
>  	};
>  };
>  
> +&pcie3a {
> +	pinctrl-0 = <&pcie3a_default>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
> +&pcie3_phy {
> +	vdda-phy-supply = <&vreg_l3c_e1_0p89>;
> +	vdda-pll-supply = <&vreg_l2c_e1_1p14>;
> +	vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>;
> +	vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>;
> +
> +	status = "okay";
> +};
> +
> +&pcie3a_port0 {
> +	vpcie12v-supply = <&vreg_pcie_12v>;
> +	vpcie3v3-supply = <&vreg_pcie_3v3>;
> +	vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>;
> +
> +	reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
> +};
> +
>  &pcie4 {
>  	pinctrl-0 = <&pcie4_default>;
>  	pinctrl-names = "default";
> @@ -590,6 +657,29 @@ ec_int_n_default: ec-int-n-state {
>  		bias-disable;
>  	};
>  
> +	pcie3a_default: pcie3a-default-state {
> +		clkreq-n-pins {
> +			pins = "gpio144";
> +			function = "pcie3a_clk";
> +			drive-strength = <2>;
> +			bias-pull-up;
> +		};
> +
> +		perst-n-pins {
> +			pins = "gpio143";
> +			function = "gpio";
> +			drive-strength = <2>;
> +			bias-disable;
> +		};
> +
> +		wake-n-pins {
> +			pins = "gpio145";
> +			function = "gpio";
> +			drive-strength = <2>;
> +			bias-pull-up;
> +		};
> +	};
> +
>  	pcie4_default: pcie4-default-state {
>  		clkreq-n-pins {
>  			pins = "gpio147";
> @@ -659,6 +749,33 @@ wake-n-pins {
>  		};
>  	};
>  
> +	pcie_x8_12v: pcie-12v-default-state {
> +		pins = "gpio26";
> +		function = "gpio";
> +		output-enable;
> +		output-high;
> +		drive-strength = <16>;
> +		bias-disable;
> +	};
> +
> +	pm_aux_3p3_en: pcie-aux-3p3-default-state {
> +		pins = "gpio136";
> +		function = "gpio";
> +		output-enable;
> +		output-high;
> +		drive-strength = <16>;
> +		bias-disable;
> +	};
> +
> +	pm_main_3p3_en: pcie-main-3p3-default-state {
> +		pins = "gpio135";
> +		function = "gpio";
> +		output-enable;
> +		output-high;
> +		drive-strength = <16>;
> +		bias-disable;
> +	};
> +
>  	wcn_wlan_bt_en: wcn-wlan-bt-en-state {
>  		pins = "gpio116", "gpio117";
>  		function = "gpio";
> 

Hey Qiang, this series conflicts with my earlier series commonizing
Glymur QCB and Mahua QCB.
Please take a look at [1] and rebase!

Best,
Sivansh

[1]: https://lore.kernel.org/all/20261027114955.1266499-4-sivansh.gupta@xxxxxxxxxxxxxxxx/

> ---
> base-commit: 8b7179210b22f8e48a82c5ceacb9d56a9c4cfec4
> change-id: 20261105-pcie3a_x8_1105-72b9c8dc1ee3
> 
> Best regards,
> --  
> Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> 
>