Re: [PATCH v3 1/3] iommu/amd: Drop unused global exclusion range fields and init

[Sairaj Kodilkar]

On 11/6/2026 2:15 PM, Jindal, Akshay wrote:
> 
> 
> On 06-11-2026 09:46, Sairaj Kodilkar wrote:
>> Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.
>>
>>
>> From: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
>>
>> Remove unused struct amd_iommu.exclusion_start/exclusion_length, the
>> MMIO_EXCL_* flag masks, and iommu_set_exclusion_range(). These struct
>> amd_iommu fields were never assigned, so early_enable_iommu() never
>> programmed the hardware exclusion registers through this path.
>>
>> Please note that the exclusion range registers have been repurposed
>> to SNP completion-wait store base / limit registers. So, rename
>> MMIO_EXCL_BASE/LIMIT via to MMIO_COMPL_STORE_BASE/LIMIT instead.
> Reviewed-by: Akshay Jindal <Akshay.Jindal@xxxxxxx>
>>
>> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
>> Signed-off-by: Sairaj Kodilkar <sarunkod@xxxxxxx>
>> Tested-by: Adam Pelka <adampelka26@xxxxxxxxx>
>> ---
>>  drivers/iommu/amd/amd_iommu_types.h | 4 ++--
>>  drivers/iommu/amd/init.c            | 6 +++---
>>  2 files changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
>> index 8241ef922519..678ceddd711c 100644
>> --- a/drivers/iommu/amd/amd_iommu_types.h
>> +++ b/drivers/iommu/amd/amd_iommu_types.h
>> @@ -44,8 +44,8 @@
>>  #define MMIO_CMD_BUF_OFFSET     0x0008
>>  #define MMIO_EVT_BUF_OFFSET     0x0010
>>  #define MMIO_CONTROL_OFFSET     0x0018
>> -#define MMIO_EXCL_BASE_OFFSET   0x0020
>> -#define MMIO_EXCL_LIMIT_OFFSET  0x0028
>> +#define MMIO_COMPL_STORE_BASE_OFFSET   0x0020
>> +#define MMIO_COMPL_STORE_LIMIT_OFFSET  0x0028
> nit:
> 1. since it is SW based re-purpose and used in function iommu_set_cwwb_range()
> suggesting renaming to MMIO_CWWB_BASE_OFFSET & MMIO_CWWB_LIMIT_OFFSET

What do you mean by SW based re-purpose. Hardware uses the register
0x0020 to store completion wait base when SNP is enabled.

The IOMMU driver always use reg 0x0020 to store the completion wait
hence I am in favour of using *EXCL* naming.

Thanks
Sairaj

>>  #define MMIO_EXT_FEATURES      0x0030
>>  #define MMIO_PPR_LOG_OFFSET    0x0038
>>  #define MMIO_GA_LOG_BASE_OFFSET        0x00e0
>> diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
>> index 8a410d4aa370..13c96feed64f 100644
>> --- a/drivers/iommu/amd/init.c
>> +++ b/drivers/iommu/amd/init.c
>> @@ -370,14 +370,14 @@ static void iommu_set_cwwb_range(struct amd_iommu *iommu)
>>          * Re-purpose Exclusion base/limit registers for Completion wait
>>          * write-back base/limit.
>>          */
>> -       memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
>> +       memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET,
>>                     &entry, sizeof(entry));
>>
>>         /* Note:
>>          * Default to 4 Kbytes, which can be specified by setting base
>>          * address equal to the limit address.
>>          */
>> -       memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
>> +       memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_LIMIT_OFFSET,
>>                     &entry, sizeof(entry));
>>  }
>>
>> @@ -1022,7 +1022,7 @@ static int __init remap_or_alloc_cwwb_sem(struct amd_iommu *iommu)
>>                  * completion wait buffer (CWB) address. Read and re-use it.
>>                  */
>>                 pr_info_once("Re-using CWB buffers from the previous kernel\n");
>> -               paddr = readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK;
>> +               paddr = readq(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET) & PM_ADDR_MASK;
>>                 iommu->cmd_sem = iommu_memremap(paddr, PAGE_SIZE);
>>                 if (!iommu->cmd_sem)
>>                         return -ENOMEM;
>> --
>> 2.34.1
>>
>>