Re: [PATCH RFC RFT v2 0/3] clk: meson: Refactor PLL pre-divider as a divider clock

[Jian Hu]

Hi Jerome,


Thanks for your review.

On 11/6/2026 1:50 AM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> > This series refactors the Meson PLL framework to remove the dedicated
> > PLL pre-divider (N) parameter from the PLL implementation and model it
> > as a separate divider clock.
> >
> > Currently, the Meson PLL framework models the PLL pre-divider using a
> > dedicated n field in struct meson_clk_pll_data. This makes the
> > pre-divider part of the PLL-specific implementation, although the
> > Common Clock Framework already provides a generic divider clock.
> >
> > The pre-divider is not intended to be dynamically adjusted. Each PLL
> > has a fixed N value as part of its configuration. Most PLLs use N = 1,
> > while a few special cases use N = 3 to satisfy their PLL input frequency
> > constraints. Modeling the pre-divider as a separate divider clock
> > removes PLL-specific handling and simplifies the PLL framework.
> s/framework/driver


Ok, I will rename framework to driver in v3.

> --
> Jerome

--

Jian