Re: [PATCH 1/5] spi: sifive: fix division by zero in clock divisor calculation

[Mark Brown]

> Clamp the divisor to 1 Hz so the divider calculation is well defined.

> +	/* A device with max_speed_hz == 0 must not divide by zero */
> +	speed_hz = max_t(u32, t->speed_hz, 1);
> +
>  	/* Calculate and program the clock rate */
> -	cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1;
> +	cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, speed_hz) - 1;
>  	cr &= SIFIVE_SPI_SCKDIV_DIV_MASK;
>  	sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);

If we did genuinely end up with a speed of 1Hz this results in only
dividing by 2, and we then truncate this to 12 bits to fit in the
register which feels a bit risky.  We should probably handle the
overflow if the result doesn't fit in the mask.

-- 
Mark Brown <broonie@xxxxxxxxxx>