Re: [PATCH 1/5] spi: sifive: fix division by zero in clock divisor calculation

[shao.mingyin]

On Mon, Nov 09, 2026 at 08:27:03PM +0000, Mark Brown wrote:
> If we did genuinely end up with a speed of 1Hz this results in only
> dividing by 2, and we then truncate this to 12 bits to fit in the
> register which feels a bit risky.  We should probably handle the
> overflow if the result doesn't fit in the mask.

Agreed.  v2 drops the 1Hz substitution: when t->speed_hz is zero the
maximum SCKDIV value is programmed directly, and a valid speed whose
divider would exceed the mask is clamped to that same value instead of
masking a truncated result.  The normal path is unchanged.

Thanks,
Shao Mingyin