Re: [PATCH v4 01/13] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGDn_VIO_DP_{TX,OTHER}

[Krzysztof Kozlowski]

On 11/11/2026 10:14, Paul Elder wrote:
> Quoting Krzysztof Kozlowski (2026-11-10 18:30:50)
>> On Mon, Nov 09, 2026 at 10:34:22PM +0900, Paul Elder wrote:
>>> Add the CPG_SGDn_VIO_DP_TX and CPG_SGDn_VIO_DP_OTHER clocks that are
>>> used by FCPV, VSP, VCON, and DPTX cores.
>>>
>>> It should be noted that there is likely a discrepancy regarding the
>>> clocks. In practice it ought not to be an issue as all the clocks derive
>>> from the same SGD1_VIO_MAIN clock and none of them are programmable or
>>> gateable.
>>>
>>> According to the datasheet, the FCPV[BID] and VSPD cores use
>>> SGD*_VIO_DP_TXφ while the VSP[BI] cores use SGD*_VIO_DP_OTHERφ.
>>> However, educated guessing suggests that IP cores in the same pipeline
>>> should be using the same clocks:
>>> - FCPV[BI] -> VSP[BI]:                  SGD*_VIO_DP_OTHERφ
>>> - FCPVD -> VSPD -> VCON -> DPTX:        SGD*_VIO_DP_TXφ
>>>
>>> Signed-off-by: Paul Elder <paul.elder+renesas@xxxxxxxxxxxxxxxx>
>>>
>>> ---
>>> Changes in v4:
>>> - Add all the clocks
>>> - remove DNI
>>
>> What is DNI?
> 
> Do not integrate. Most of the patches here were DNI in previous versions
> because they depended on a lot of downstream things, but now those dependencies
> are in the process of upstreaming so these can graduate from DNI status.

Upstream clock indices ABI does not depend on downstream at all, so
seeing this unmergeable is just confusing.

Best regards,
Krzysztof