OK. Just one CONFIG_PCI_QUIRKS is probably the best bet then.
> > >Please let me know whether it does the trick.
> > >
> >
> > Works fine on 2.1.78. Not sure how many bios's have this problem.
> > I checked two SuperMicro motherboards (a P6SNE and a P6DNE with
> > AMI bios) and both of them failed to set the passive release
> > bit correctly.
>
>Good.
>
>I have an Intel Venus MB, with the relevant PCI chipset, and an AMI
>BIOS, and I don't have the problem. I got the machine around october
>'96, so presumably AMI had sorted it out by then.
>
The P6SNE was purchased around a year ago -- the bios was flashed a
month ago with the latest version posted at their web site. The other
board is a brand new P6DNE so maybe this is a SuperMicro specific problem.
Anyone else out there with a SuperMicro board who can confirm this?
BTW -- when you say that you don't have the problem do you mean that
passive release is already enabled on your board? Aaccording to the
Intel document the problem occurs when "The USWC Write Posting during I/O
bridge access enable (UWPIO) bit is set to 1. This bit is located in
DBC (DBX Buffer Control) bit #5 in PMC at address offset 53h."
This bit seems to be controlled by the write posting/combining settings
in the bios -- If I shut these off the bit isn't set but the video
performance is poor even with the mtrr patch which I guess makes
sense because write combining is off even if the mtrr region is set up.
Emil
>--
>Dave Wragg
>