RE: [PATCH net-next v5 1/4] dpll: add DPLL_PIN_TYPE_INT_NCO pin type

[Kubalewski, Arkadiusz]

>From: Ivan Vecera <ivecera@xxxxxxxxxx>
>Sent: Sunday, May 31, 2026 9:44 PM
>
>Add DPLL_PIN_TYPE_INT_NCO pin type for virtual pins representing the NCO
>mode of a DPLL. When connected as a DPLL input, the DPLL enters NCO mode
>where the output frequency is adjusted by the host via the PTP clock
>interface.
>
>Update the fractional-frequency-offset and fractional-frequency- offset-
>ppt attribute documentation to note that for INT_NCO pins these attributes
>represent the DPLL's current output frequency offset from its nominal
>frequency.
>
>Reviewed-by: Jiri Pirko <jiri@xxxxxxxxxx>
>Signed-off-by: Ivan Vecera <ivecera@xxxxxxxxxx>
>---
>v2:
>  - Clarify int-nco pin type documentation to describe frequency
>    control via the PTP clock interface instead of generic "controlled
>    by the host".
>  - Tighten FFO attribute documentation for INT_NCO pins to describe
>    the DPLL's output frequency offset from nominal frequency.
>  - Mention both fractional-frequency-offset (PPM) and
>    fractional-frequency-offset-ppt attributes in the commit message.
>---
> Documentation/netlink/specs/dpll.yaml | 13 +++++++++++++
> drivers/dpll/dpll_nl.c                |  2 +-
> include/uapi/linux/dpll.h             |  4 ++++
> 3 files changed, 18 insertions(+), 1 deletion(-)
>
>diff --git a/Documentation/netlink/specs/dpll.yaml
>b/Documentation/netlink/specs/dpll.yaml
>index 91a172617b3a9..5cdb93e8649a0 100644
>--- a/Documentation/netlink/specs/dpll.yaml
>+++ b/Documentation/netlink/specs/dpll.yaml
>@@ -162,6 +162,13 @@ definitions:
>       -
>         name: gnss
>         doc: GNSS recovered clock
>+      -
>+        name: int-nco
>+        doc: |
>+          Device internal numerically controlled oscillator.
>+          When connected as a DPLL input, the DPLL enters NCO mode
>+          where the output frequency is adjusted by the host via
>+          the PTP clock interface.

Hi Ivan!

How would you control this in case of automatic mode dpll?
Automatic mode DPLL shall be controlled on HW level, such pin brakes
that rule and requires some driver magic to show it is higher
priority then the rest of the pins?

Such NCO mode/pin is designed only for this single specific use case
where a timecard contains a DPLL and PHC?

Any diagram?

Is there any other use case for such pin? (NCO is rather a general
DPLL control mechanism?) Shouldn't it be called explicitly like
ptp-nco?

Thank you!
Arkadiusz

>     render-max: true
>   -
>     type: enum
>@@ -453,6 +460,9 @@ attribute-sets:
>           offset on the media associated with the pin. Inside
>           the pin-parent-device nest it represents the frequency
>           offset between the pin and its parent DPLL device.
>+          For pins of type PIN_TYPE_INT_NCO this represents
>+          the DPLL's current output frequency offset from its
>+          nominal frequency.
>           Value is in PPM (parts per million).
>           This is a lower-precision version of
>           fractional-frequency-offset-ppt.
>@@ -499,6 +509,9 @@ attribute-sets:
>           offset on the media associated with the pin. Inside
>           the pin-parent-device nest it represents the frequency
>           offset between the pin and its parent DPLL device.
>+          For pins of type PIN_TYPE_INT_NCO this represents
>+          the DPLL's current output frequency offset from its
>+          nominal frequency.
>           Value is in PPT (parts per trillion, 10^-12).
>           This is a higher-precision version of
>           fractional-frequency-offset.
>diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c index
>b1d9182c7802f..2dab99202764f 100644
>--- a/drivers/dpll/dpll_nl.c
>+++ b/drivers/dpll/dpll_nl.c
>@@ -61,7 +61,7 @@ static const struct nla_policy
>dpll_pin_id_get_nl_policy[DPLL_A_PIN_TYPE + 1] =
> 	[DPLL_A_PIN_BOARD_LABEL] = { .type = NLA_NUL_STRING, },
> 	[DPLL_A_PIN_PANEL_LABEL] = { .type = NLA_NUL_STRING, },
> 	[DPLL_A_PIN_PACKAGE_LABEL] = { .type = NLA_NUL_STRING, },
>-	[DPLL_A_PIN_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 5),
>+	[DPLL_A_PIN_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 6),
> };
>
> /* DPLL_CMD_PIN_GET - do */
>diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h index
>cb363cccf2e2a..9245827de3cfd 100644
>--- a/include/uapi/linux/dpll.h
>+++ b/include/uapi/linux/dpll.h
>@@ -127,6 +127,9 @@ enum dpll_type {
>  * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock
>  * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator
>  * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock
>+ * @DPLL_PIN_TYPE_INT_NCO: Device internal numerically controlled
>oscillator.
>+ *   When connected as a DPLL input, the DPLL enters NCO mode where the
>output
>+ *   frequency is adjusted by the host via the PTP clock interface.
>  */
> enum dpll_pin_type {
> 	DPLL_PIN_TYPE_MUX = 1,
>@@ -134,6 +137,7 @@ enum dpll_pin_type {
> 	DPLL_PIN_TYPE_SYNCE_ETH_PORT,
> 	DPLL_PIN_TYPE_INT_OSCILLATOR,
> 	DPLL_PIN_TYPE_GNSS,
>+	DPLL_PIN_TYPE_INT_NCO,
>
> 	/* private: */
> 	__DPLL_PIN_TYPE_MAX,
>--
>2.53.0