Re: [PATCH v2] arm64: dts: qcom: sm8550: add SDHC4 controller node

[William Bright]

On Thu, Jun 04, 2026 at 07:01:22PM +0300, Vladimir Zapolskiy wrote:
> 
> How do you know that these modes are broken in hardware and not
> caused by something else?
> 
> It was stated before, but it was proven to be invalid as the statement.
> 
Thanks Vladimir for your feedback.

I copied this statement from when these modes were also masked out on
sdhc_2. I see that there was progress since then and the caps mask has
been dropped so I agree that I shouldn't have this comment that these
modes are broken due to hardware.

I have tested this patch after rebasing onto the latest tree with the
recent changes that allowed for the caps mask to be dropped for sdhc_2
and I still see dll tuning failing. To progress, I need some guidance
from qcom as to what dll-config value should be used as I am uncertain
about this. I noticed that ftbl_gcc_sdcc4_apps_clk_src only goes up to
75MHz so perhaps this needs modifying for DLL-tuning to pass and maybe
there needs to be schematic/routing guidance that needs to be strictly
followed as-well besides the usual 50 ohm impedance rules?
> > - Forbid SDR104/SDR50 via sdhci-caps-mask, matching the previously
> >    existing sdhc_2 workaround in the same file.
> >    The SDHCI capabilities register on this SoC advertises SDR50/SDR104
> >    modes that are broken on sdhc_4; without masking them the MMC
> >    core selects SDR50 and fails DLL tuning with
> >    -ETIMEDOUT during SDIO card initialisation.
> 
> Which one SDIO card do you test?
> 
My apologies, I made a mistake in the cover letter, I wasn't testing with
an SDIO card, I was testing with an NXP IW416 which is hard-wired to
sdhc_4. 

Best regards,

Will