Re: [PATCH v2] arm64: dts: qcom: sm8550: add SDHC4 controller node

[Vladimir Zapolskiy]

On 6/9/26 19:21, William Bright wrote:
> On Thu, Jun 04, 2026 at 07:01:22PM +0300, Vladimir Zapolskiy wrote:
> > How do you know that these modes are broken in hardware and not
> > caused by something else?
> >
> > It was stated before, but it was proven to be invalid as the statement.
> Thanks Vladimir for your feedback.
>
> I copied this statement from when these modes were also masked out on
> sdhc_2. I see that there was progress since then and the caps mask has
> been dropped so I agree that I shouldn't have this comment that these
> modes are broken due to hardware.

Well, it might be broken due to hardware, but not necessarily due to
Qualcomm SoC IP, there is a chance of a PCB design flaw.

> I have tested this patch after rebasing onto the latest tree with the
> recent changes that allowed for the caps mask to be dropped for sdhc_2
> and I still see dll tuning failing. To progress, I need some guidance
> from qcom as to what dll-config value should be used as I am uncertain
> about this. I noticed that ftbl_gcc_sdcc4_apps_clk_src only goes up to
> 75MHz so perhaps this needs modifying for DLL-tuning to pass and maybe
> there needs to be schematic/routing guidance that needs to be strictly
> followed as-well besides the usual 50 ohm impedance rules?
> > > - Forbid SDR104/SDR50 via sdhci-caps-mask, matching the previously
> > >     existing sdhc_2 workaround in the same file.
> > >     The SDHCI capabilities register on this SoC advertises SDR50/SDR104
> > >     modes that are broken on sdhc_4; without masking them the MMC
> > >     core selects SDR50 and fails DLL tuning with
> > >     -ETIMEDOUT during SDIO card initialisation.
> >
> > Which one SDIO card do you test?
> My apologies, I made a mistake in the cover letter, I wasn't testing with
> an SDIO card, I was testing with an NXP IW416 which is hard-wired to
> sdhc_4.

FWIW due to https://www.nxp.com/docs/en/data-sheet/IW416.pdf "10.7.1 VIO_SD
DC characteristics" SDR104 speed mode is not supported by the module, thus
the selection of the SDR50 speed mode on the host side sounds to be correct
in your case.

In SDR50 speed mode gcc_sdcc4_apps_clk clock frequency should be exactly
100MHz, and since it differs, it has an impact during the tuning phase.

Definitely clk/qcom/gcc-sm8550.c says that the maximum supported frequency
is 75MHz, the same is found in the downstream v5.15 kernel:

static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
        F(400000, P_BI_TCXO, 12, 1, 4),
        F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
        F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
        F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
        { }
};

Can you dump CAPS1 register value of SM8550 SDHC4? What does it say about
SDR50 mode support and need for SDR50 mode tuning?

--
Best wishes,
Vladimir