Re: [PATCH v4 2/3] spi: tegra210-quad: Cache TRANS_STATUS in ISR for timeout handler

[Mark Brown]

On Wed, Jun 10, 2026 at 06:24:01AM +0000, Vishwaroop A wrote:

>   - tegra_qspi_isr() reads QSPI_FIFO_STATUS and QSPI_TRANS_STATUS,
>     derives tx_status / rx_status, then publishes them via WRITE_ONCE()
>     and the trans_status cache via smp_store_release() before masking
>     and acking the controller IRQ.

>   - tegra_qspi_handle_timeout() consumes trans_status with a paired
>     smp_load_acquire(). The release/acquire pair guarantees that a
>     timeout handler which observes a non-zero trans_status also
>     observes the matching status_reg / tx_status / rx_status updates.

>   - tegra_qspi_setup_transfer_one() clears the cache with
>     smp_store_release() under the spinlock before unmasking the IRQ
>     for the new transfer, so a stale RDY bit from the previous
>     transfer cannot fool the timeout handler.

It looks like the CPU based transfer function supports multiple
interrupts per transfer, though the copybreak for switching to DMA is
FIFO sized so I'm not clear exactly when that might happen.  Can that
happen, and if so don't we need to clear trans_status when we handle the
interrupt as well?  It might be that this can't actually happen.

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