[PATCH 3/5] pinctrl: samsung: Add Exynos8855 pinctrl configuration
From: Alim Akhtar
Date: Fri Jun 12 2026 - 12:15:39 EST
Add pinctrl configuration for Exynos8855. The bank type
macros are reused from Exynos850 SoC.
Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
---
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 124 ++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 127 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index fe9f92cb037e..ba2a11f8e19d 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -943,6 +943,130 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
.num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl),
};
+/* pin banks of exynos8855 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks0[] __initconst = {
+ /* Must start with EINTG banks, ordered by EINT group number. */
+ EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+ EXYNOS850_PIN_BANK_EINTW(4, 0x020, "gpa1", 0x04),
+ EXYNOS850_PIN_BANK_EINTN(3, 0x040, "gpq0"),
+ EXYNOS850_PIN_BANK_EINTN(2, 0x060, "gpq1"),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpc0", 0x10),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpc1", 0x14),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpc2", 0x18),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpc3", 0x1c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpc4", 0x20),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpc5", 0x24),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpc6", 0x28),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpc7", 0x2c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpc8", 0x30),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1a0, "gpc9", 0x34),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpc10", 0x38),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpc11", 0x3c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpc12", 0x40),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpc13", 0x44),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpc14", 0x48),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpj0", 0x4c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpj1", 0x50),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpj2", 0x54),
+};
+
+/* pin banks of exynos8855 pin-controller 1 (CMGP) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks1[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTW(1, 0x00, "gpm0", 0x00),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x20, "gpm1", 0x04),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x40, "gpm2", 0x08),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x60, "gpm3", 0x0c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x80, "gpm4", 0x10),
+ EXYNOS850_PIN_BANK_EINTW(1, 0xa0, "gpm5", 0x14),
+ EXYNOS850_PIN_BANK_EINTW(1, 0xc0, "gpm6", 0x18),
+ EXYNOS850_PIN_BANK_EINTW(1, 0xe0, "gpm7", 0x1c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1a0, "gpm13", 0x34),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpm21", 0x54),
+};
+
+
+/* pin banks of exynos8855 pin-controller 2 (HSI UFS) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks2[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gpf3", 0x00),
+};
+
+/* pin banks of exynos8855 pin-controller 3 (PERIC) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks3[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp0", 0x00),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpp1", 0x04),
+ EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gpp2", 0x08),
+ EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpg0", 0x0c),
+ EXYNOS850_PIN_BANK_EINTG(3, 0x80, "gpg1", 0x10),
+ EXYNOS850_PIN_BANK_EINTG(6, 0xa0, "gpb0", 0x14),
+ EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpb1", 0x18),
+};
+
+/* pin banks of exynos8855 pin-controller 4 (PERICMMC) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks4[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpf2", 0x00),
+};
+
+/* pin banks of exynos8855 pin-controller 5 (USI) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks5[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(8, 0x00, "gpp3", 0x00),
+ EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gpp4", 0x04),
+ EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpg2", 0x08),
+ EXYNOS850_PIN_BANK_EINTG(1, 0x60, "gpg3", 0x0c),
+};
+
+static const struct samsung_pin_ctrl exynos8855_pin_ctrl[] __initconst = {
+ {
+ /* pin-controller instance 0 ALIVE data */
+ .pin_banks = exynos8855_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 1 CMGP data */
+ .pin_banks = exynos8855_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks1),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 2 HSI UFS data */
+ .pin_banks = exynos8855_pin_banks2,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks2),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 3 PERIC data */
+ .pin_banks = exynos8855_pin_banks3,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks3),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 4 PERICMMC data */
+ .pin_banks = exynos8855_pin_banks4,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks4),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 5 USI data */
+ .pin_banks = exynos8855_pin_banks5,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks5),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ },
+};
+
+const struct samsung_pinctrl_of_match_data exynos8855_of_data __initconst = {
+ .ctrl = exynos8855_pin_ctrl,
+ .num_ctrl = ARRAY_SIZE(exynos8855_pin_ctrl),
+};
+
/* pin banks of exynos990 pin-controller 0 (ALIVE) */
static struct samsung_pin_bank_data exynos990_pin_banks0[] = {
/* Must start with EINTG banks, ordered by EINT group number. */
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 5ac6f6b02327..5ecc9ed4c44d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1500,6 +1500,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = &exynos7885_of_data },
{ .compatible = "samsung,exynos850-pinctrl",
.data = &exynos850_of_data },
+ { .compatible = "samsung,exynos8855-pinctrl",
+ .data = &exynos8855_of_data },
{ .compatible = "samsung,exynos8890-pinctrl",
.data = &exynos8890_of_data },
{ .compatible = "samsung,exynos8895-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 937600430a6e..bb02fb49b2af 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -396,6 +396,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
+extern const struct samsung_pinctrl_of_match_data exynos8855_of_data;
extern const struct samsung_pinctrl_of_match_data exynos8890_of_data;
extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
extern const struct samsung_pinctrl_of_match_data exynos9610_of_data;
--
2.34.1