[tip:x86/asm 2/4] arch/x86/include/asm/special_insns.h:31:9: error: 'X86_CR0_WP' undeclared

[kbuild test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/asm
head:   a0bf7fc24303a538396aa8d32450d05c1929b9f0
commit: d309ba034fac1a149d00cac79318973e9ba81848 [2/4] x86/asm: Pin sensitive CR0 bits
config: um-x86_64_defconfig (attached as .config)
compiler: gcc-8 (Debian 8.3.0-2) 8.3.0
reproduce:
        git checkout d309ba034fac1a149d00cac79318973e9ba81848
        # save the attached .config to linux build tree
        make ARCH=um SUBARCH=x86_64

All errors (new ones prefixed by >>):

   In file included from arch/x86/include/asm/cacheflush.h:7,
                    from include/linux/highmem.h:12,
                    from net//core/sock.c:117:
   arch/x86/include/asm/special_insns.h: In function 'native_write_cr0':
>> arch/x86/include/asm/special_insns.h:31:9: error: 'X86_CR0_WP' undeclared (first use in this function)
     val |= X86_CR0_WP;
            ^~~~~~~~~~
   arch/x86/include/asm/special_insns.h:31:9: note: each undeclared identifier is reported only once for each function it appears in
--
   In file included from arch/x86/include/asm/cacheflush.h:7,
                    from include/linux/highmem.h:12,
                    from net//ipv4/ip_output.c:52:
   arch/x86/include/asm/special_insns.h: In function 'native_write_cr0':
>> arch/x86/include/asm/special_insns.h:31:9: error: 'X86_CR0_WP' undeclared (first use in this function); did you mean 'X86_BUG_11AP'?
     val |= X86_CR0_WP;
            ^~~~~~~~~~
            X86_BUG_11AP
   arch/x86/include/asm/special_insns.h:31:9: note: each undeclared identifier is reported only once for each function it appears in

vim +/X86_CR0_WP +31 arch/x86/include/asm/special_insns.h

    25	
    26	static inline void native_write_cr0(unsigned long val)
    27	{
    28		bool warn = false;
    29	
    30	again:
  > 31		val |= X86_CR0_WP;
    32		/*
    33		 * In order to have the compiler not optimize away the check
    34		 * after the cr4 write, mark "val" as being also an output ("+r")
    35		 * by this asm() block so it will perform an explicit check, as
    36		 * if it were "volatile".
    37		 */
    38		asm volatile("mov %0,%%cr0" : "+r" (val) : "m" (__force_order) : );
    39		/*
    40		 * If the MOV above was used directly as a ROP gadget we can
    41		 * notice the lack of pinned bits in "val" and start the function
    42		 * from the beginning to gain the WP bit for sure. And do it
    43		 * without first taking the exception for a WARN().
    44		 */
    45		if ((val & X86_CR0_WP) != X86_CR0_WP) {
    46			warn = true;
    47			goto again;
    48		}
    49		WARN_ONCE(warn, "Attempt to unpin X86_CR0_WP, cr0 bypass attack?!\n");
    50	}
    51	

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