Re: [PATCH V5 11/18] clk: tegra210: Add support for Tegra210 clocks

[Sowjanya Komatineni]

On 7/18/19 12:18 PM, Peter De Schrijver wrote:
> On Tue, Jul 16, 2019 at 09:43:16PM +0300, Dmitry Osipenko wrote:
> > > CPU parents are PLL_X, PLL_P, and dfll. PLL_X always runs at higher rate
> > > so switching to PLL_P during CPUFreq probe prior to dfll clock enable
> > > should be safe.
> > AFAIK, PLLX could run at ~200MHz. There is also a divided output of PLLP
> > which CCLKG supports, the PLLP_OUT4.
> >
> > Probably, realistically, CPU is always running off a fast PLLX during
> > boot, but I'm wondering what may happen on KEXEC. I guess ideally
> > CPUFreq driver should also have a 'shutdown' callback to teardown DFLL
> > on a reboot, but likely that there are other clock-related problems as
> > well that may break KEXEC and thus it is not very important at the moment.
> If you turn off the DFLL, you have to be aware that the voltage margins
> for DFLL use are lower than for PLL use. So you either need to be sure
> to switch to a frequency below fmax @ Vmin or you program the boot
> voltage and then you can use PLLX as setup by the bootloader. For OVR
> regulators you can't program a voltage without the DFLL, so you have to
> tristate the PWM output which will give you a hardwired boot voltage.
>
> Peter.

Yes, we switch CPU to PLLP and then disable DFLL during suspend.