22.07.2019 6:17, Sowjanya Komatineni ÐÐÑÐÑ:
On 7/21/19 3:39 PM, Sowjanya Komatineni wrote:The TRM doc says "The CPU subsystem supports a switch-cluster mode
On 7/21/19 2:16 PM, Dmitry Osipenko wrote:Though to avoid flag and check needed to make sure other CPU is not
21.07.2019 22:40, Sowjanya Komatineni ÐÐÑÐÑ:PLLP may be used for other CPU clusters.
This patch has a fix to enable PLLP branches to CPU before changingShould somewhere here be tegra_clk_set_pllp_out_cpu(false) when
the CPU clusters clock source to PLLP for Gen5 Super clock.
During system suspend entry and exit, CPU source will be switched
to PLLP and this needs PLLP branches to be enabled to CPU prior to
the switch.
On system resume, warmboot code enables PLLP branches to CPU and
powers up the CPU with PLLP clock source.
Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx>
---
 drivers/clk/tegra/clk-super.c | 11 +++++++++++
 drivers/clk/tegra/clk-tegra-super-gen4.c | 4 ++--
 drivers/clk/tegra/clk.h | 4 ++++
 3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-super.c
b/drivers/clk/tegra/clk-super.c
index 39ef31b46df5..d73c587e4853 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -28,6 +28,9 @@
 #define super_state_to_src_shift(m, s) ((m->width * s))
 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
 +#define CCLK_SRC_PLLP_OUT0 4
+#define CCLK_SRC_PLLP_OUT4 5
+
 static u8 clk_super_get_parent(struct clk_hw *hw)
 {
ÂÂÂÂÂ struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
@@ -97,6 +100,14 @@ static int clk_super_set_parent(struct clk_hw
*hw, u8 index)
ÂÂÂÂÂÂÂÂÂ if (index == mux->div2_index)
ÂÂÂÂÂÂÂÂÂÂÂÂÂ index = mux->pllx_index;
ÂÂÂÂÂ }
+
+ÂÂÂ /*
+ÂÂÂÂ * Enable PLLP branches to CPU before selecting PLLP source
+ÂÂÂÂ */
+ÂÂÂ if ((mux->flags & TEGRA_CPU_CLK) &&
+ÂÂÂÂÂÂÂ ((index == CCLK_SRC_PLLP_OUT0) || (index ==
CCLK_SRC_PLLP_OUT4)))
+ÂÂÂÂÂÂÂ tegra_clk_set_pllp_out_cpu(true);
switching from PLLP?
using before disabling PLLP branch to CPU.
But leaving it enabled shouldn't impact much as clock source mux is
after this in design anyway.
But can add as well if its clear that way.
meaning that only one of the clusters can be active at any given time".
Given that cluster-switching isn't supported in upstream, I don't think
that you need to care about the other cluster at all, at least for now.
The cluster-switching implementation in upstream is very complicated
because it requires a special "hotplugging" CPU governor, which
apparently no other platform needs.
[snip]