Re: [PATCH V2] perf vendor events riscv: add T-HEAD C9xx JSON file

[Inochi Amaoto]

> Please put change log and example between
> ---
> ---
>
> So it will look like:
>
> > Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxxxx>
> > ---
> ----> changelog here
> ----> example here
> > ---
> > tools/perf/pmu-events/arch/riscv/mapfile.csv  |  1 +
>
> Otherwise it's too verbose and contains stuff related to OpenSBI and
> not the perf itself.
>
> Also checkpatch show some minor problems.
>
> Also i think a mentioning c906,c910,c920 in commit message and
> providing a brief information about their difference.

Will fix in V3

> > event id range   |  support cpu
> > 0x01 - 0x06     |  c906,c910,c920
> > 0x07            |  c906
>
> I don't see it in the json file.

0x01 - 0x05 are in cache.json
0x06 - 0x07 should in instruction.json

I will fix the left 0x07 and its name in the V3.

> > 0x08 - 0x0a     |  c910,c920
> > 0x0b - 0x0f     |  c906,c910,c920
> > 0x10 - 0x1a     |  c910,c920
> > 0x1b - 0x1c     |  c910,c920 (software defined, >= 0x1b)
> > 0x1d - 0x2a     |  c906
>
> So is this a complete list for c906 ?

This is a complete list for the whole T-HEAD c9xx series until now.
Some of the events can be used in c906 (the line has c906 in the table).

> I ll test it soon then, however:
>
> 1) What version of OpenSBI is used ?
> 2) What platforms have you tested ?

The mainline OpenSBI is just OK.

I have test this on a sophgo sg2042 board (c920).
This pmu node is just fine for both c910 and c920.
But c906 should change some events as it does not support.