RE: [PATCH] arm64: zynqmp: Switch to amd.com emails
From: Paladugu, Siva Durga Prasad
Date: Wed May 17 2023 - 07:57:58 EST
> -----Original Message-----
> From: Simek, Michal <michal.simek@xxxxxxx>
> Sent: Tuesday, May 16, 2023 7:12 PM
> To: linux-kernel@xxxxxxxxxxxxxxx; monstr@xxxxxxxxx; michal.simek@xxxxxxxxxx;
> git@xxxxxxxxxx
> Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@xxxxxxxxxx>; Andrew Davis
> <afd@xxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>; Geert Uytterhoeven
> <geert+renesas@xxxxxxxxx>; Katakam, Harini <harini.katakam@xxxxxxx>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx>; Laurent Pinchart
> <laurent.pinchart@xxxxxxxxxxxxxxxx>; Michael Grzeschik
> <m.grzeschik@xxxxxxxxxxxxxx>; Michael Tretter <m.tretter@xxxxxxxxxxxxxx>;
> Gajjar, Parth <parth.gajjar@xxxxxxx>; Piyush Mehta
> <piyush.mehta@xxxxxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>; Robert
> Hancock <robert.hancock@xxxxxxxxxx>; Srinivas Neeli
> <srinivas.neeli@xxxxxxxxxx>; Shah, Tanmay <tanmay.shah@xxxxxxx>; Sagar,
> Vishal <vishal.sagar@xxxxxxx>; devicetree@xxxxxxxxxxxxxxx; linux-arm-
> kernel@xxxxxxxxxxxxxxxxxxx
> Subject: [PATCH] arm64: zynqmp: Switch to amd.com emails
>
> Update my and DPs email address to match current setup.
>
> Signed-off-by: Michal Simek <michal.simek@xxxxxxx>
> ---
>
> arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts | 5 +++--
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 7 ++++---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++--
> 24 files changed, 51 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> index 88aa06fa78a8..1495272e5668 100644
> --- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> +++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Avnet Ultra96 rev1
> *
> - * (C) Copyright 2018, Xilinx, Inc.
> + * (C) Copyright 2018 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xxxxxxxxxx>
> + * Michal Simek <michal.simek@xxxxxxx>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> index 719ea5d5ae88..f04716841a0c 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> @@ -5,7 +5,7 @@
> * (C) Copyright 2017 - 2022, Xilinx, Inc.
> * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xxxxxxxxxx>
> + * Michal Simek <michal.simek@xxxxxxx>
> */
>
> #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> index bebbe955eec1..669fe6084f3f 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> @@ -9,7 +9,7 @@
> * "Y" - A01 board modified with legacy interposer (Nexperia)
> * "Z" - A01 board modified with Diode interposer
> *
> - * Michal Simek <michal.simek@xxxxxxxxxx>
> + * Michal Simek <michal.simek@xxxxxxx>
> */
>
> #include <dt-bindings/gpio/gpio.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> index 8e66448f35a9..7886a19139ee 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> @@ -4,7 +4,7 @@
> *
> * (C) Copyright 2020 - 2021, Xilinx, Inc.
> *
> - * Michal Simek <michal.simek@xxxxxxxxxx>
> + * Michal Simek <michal.simek@xxxxxxx>
> */
>
> #include <dt-bindings/gpio/gpio.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> index 464e28bf078a..8d1c54e00556 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
> *
> - * (C) Copyright 2020 - 2021, Xilinx, Inc.
> + * (C) Copyright 2020 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xxxxxxxxxx>
> + * Michal Simek <michal.simek@xxxxxxx>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> index c70966c1f344..664ea7d99049 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
> *
> - * (C) Copyright 2020 - 2021, Xilinx, Inc.
> + * (C) Copyright 2020 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xxxxxxxxxx>
> + * Michal Simek <michal.simek@xxxxxxx>
> */
>
> #include "zynqmp-sm-k26-revA.dts"
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> index f1598527e5ec..774fb773886e 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> @@ -2,9 +2,10 @@
> /*
> * dts file for Xilinx ZynqMP ZC1232
> *
> - * (C) Copyright 2017 - 2021, Xilinx, Inc.
> + * (C) Copyright 2017 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xxxxxxxxxx>
> + * Michal Simek <michal.simek@xxxxxxx>
> */
>
> /dts-v1/;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> index 04efa1683eaa..7c27b0e9a522 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> @@ -2,10 +2,11 @@
> /*
> * dts file for Xilinx ZynqMP ZC1254
> *
> - * (C) Copyright 2015 - 2021, Xilinx, Inc.
> + * (C) Copyright 2015 - 2022, Xilinx, Inc.
> + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> *
> - * Michal Simek <michal.simek@xxxxxxxxxx>
> - * Siva Durga Prasad Paladugu <sivadur@xxxxxxxxxx>
> + * Michal Simek <michal.simek@xxxxxxx>
> + * Siva Durga Prasad Paladug <siva.durga.prasad.paladugu@xxxxxxx>
There is a typo in my name here and everywhere in the patch, Please fix this. Paladug -> Paladugu
Thanks,
DP