Re: [PATCH 1/2] cpufreq/amd-pstate: Write CPPC enable bit for each core
From: Huang Rui
Date: Mon May 22 2023 - 04:18:21 EST
On Mon, May 22, 2023 at 02:33:24PM +0800, Karny, Wyes wrote:
> ACPI specification [1] says: "CPPC Enable Register: If supported by the
> platform, OSPM writes a one to this register to enable CPPC on this
> processor."
>
> Make amd_pstate align with the specification.
>
> To do so, move amd_pstate_enable function to per-policy/per-core
> callbacks.
>
> Also remove per-cpu loop from cppc_enable, because it's called from
> per-policy/per-core callbacks and it was causing duplicate MSR writes.
> This will improve driver-load, suspend-resume and offline-online on
> shared memory system.
>
> [1]: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/08_Processor_Configuration_and_Control/declaring-processors.html#cppc-enable-register
>
> Fixes: e059c184da47 ("cpufreq: amd-pstate: Introduce the support for the processors with shared memory solution")
> Signed-off-by: Wyes Karny <wyes.karny@xxxxxxx>
> ---
> drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++------------------
> 1 file changed, 26 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 5a3d4aa0f45a..8c72f95ac315 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -226,29 +226,27 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
> return ret;
> }
>
> -static inline int pstate_enable(bool enable)
> +static inline int pstate_enable(int cpu, bool enable)
> {
> - return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable);
> + return wrmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_ENABLE, enable);
In the full MSR processors, the CPPCEnableRegister is per package, not per
thread. In share memory processors, it should be per thread.
Thanks,
Ray
> }
>
> -static int cppc_enable(bool enable)
> +static int cppc_enable(int cpu, bool enable)
> {
> - int cpu, ret = 0;
> + int ret = 0;
> struct cppc_perf_ctrls perf_ctrls;
>
> - for_each_present_cpu(cpu) {
> - ret = cppc_set_enable(cpu, enable);
> + ret = cppc_set_enable(cpu, enable);
> + if (ret)
> + return ret;
> +
> + /* Enable autonomous mode for EPP */
> + if (cppc_state == AMD_PSTATE_ACTIVE) {
> + /* Set desired perf as zero to allow EPP firmware control */
> + perf_ctrls.desired_perf = 0;
> + ret = cppc_set_perf(cpu, &perf_ctrls);
> if (ret)
> return ret;
> -
> - /* Enable autonomous mode for EPP */
> - if (cppc_state == AMD_PSTATE_ACTIVE) {
> - /* Set desired perf as zero to allow EPP firmware control */
> - perf_ctrls.desired_perf = 0;
> - ret = cppc_set_perf(cpu, &perf_ctrls);
> - if (ret)
> - return ret;
> - }
> }
>
> return ret;
> @@ -256,9 +254,9 @@ static int cppc_enable(bool enable)
>
> DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable);
>
> -static inline int amd_pstate_enable(bool enable)
> +static inline int amd_pstate_enable(int cpu, bool enable)
> {
> - return static_call(amd_pstate_enable)(enable);
> + return static_call(amd_pstate_enable)(cpu, enable);
> }
>
> static int pstate_init_perf(struct amd_cpudata *cpudata)
> @@ -643,6 +641,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
>
> cpudata->cpu = policy->cpu;
>
> + ret = amd_pstate_enable(policy->cpu, true);
> +
> ret = amd_pstate_init_perf(cpudata);
> if (ret)
> goto free_cpudata1;
> @@ -724,7 +724,7 @@ static int amd_pstate_cpu_resume(struct cpufreq_policy *policy)
> {
> int ret;
>
> - ret = amd_pstate_enable(true);
> + ret = amd_pstate_enable(policy->cpu, true);
> if (ret)
> pr_err("failed to enable amd-pstate during resume, return %d\n", ret);
>
> @@ -735,7 +735,7 @@ static int amd_pstate_cpu_suspend(struct cpufreq_policy *policy)
> {
> int ret;
>
> - ret = amd_pstate_enable(false);
> + ret = amd_pstate_enable(policy->cpu, false);
> if (ret)
> pr_err("failed to disable amd-pstate during suspend, return %d\n", ret);
>
> @@ -841,7 +841,6 @@ static ssize_t show_energy_performance_preference(
>
> static void amd_pstate_driver_cleanup(void)
> {
> - amd_pstate_enable(false);
> cppc_state = AMD_PSTATE_DISABLE;
> current_pstate_driver = NULL;
> }
> @@ -1039,6 +1038,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
> cpudata->cpu = policy->cpu;
> cpudata->epp_policy = 0;
>
> + ret = amd_pstate_enable(policy->cpu, true);
> +
> ret = amd_pstate_init_perf(cpudata);
> if (ret)
> goto free_cpudata1;
> @@ -1180,13 +1181,13 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
> return 0;
> }
>
> -static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
> +static void amd_pstate_epp_reenable(int cpu, struct amd_cpudata *cpudata)
> {
> struct cppc_perf_ctrls perf_ctrls;
> u64 value, max_perf;
> int ret;
>
> - ret = amd_pstate_enable(true);
> + ret = amd_pstate_enable(cpu, true);
> if (ret)
> pr_err("failed to enable amd pstate during resume, return %d\n", ret);
>
> @@ -1209,7 +1210,7 @@ static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
> pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);
>
> if (cppc_state == AMD_PSTATE_ACTIVE) {
> - amd_pstate_epp_reenable(cpudata);
> + amd_pstate_epp_reenable(policy->cpu, cpudata);
> cpudata->suspended = false;
> }
>
> @@ -1280,7 +1281,7 @@ static int amd_pstate_epp_suspend(struct cpufreq_policy *policy)
> cpudata->suspended = true;
>
> /* disable CPPC in lowlevel firmware */
> - ret = amd_pstate_enable(false);
> + ret = amd_pstate_enable(policy->cpu, false);
> if (ret)
> pr_err("failed to suspend, return %d\n", ret);
>
> @@ -1295,7 +1296,7 @@ static int amd_pstate_epp_resume(struct cpufreq_policy *policy)
> mutex_lock(&amd_pstate_limits_lock);
>
> /* enable amd pstate from suspend state*/
> - amd_pstate_epp_reenable(cpudata);
> + amd_pstate_epp_reenable(policy->cpu, cpudata);
>
> mutex_unlock(&amd_pstate_limits_lock);
>
> @@ -1370,8 +1371,6 @@ static int __init amd_pstate_init(void)
> static_call_update(amd_pstate_update_perf, cppc_update_perf);
> }
>
> - /* enable amd pstate feature */
> - ret = amd_pstate_enable(true);
> if (ret) {
> pr_err("failed to enable with return %d\n", ret);
> return ret;
> --
> 2.34.1
>