[PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling

[Terry Bowman]

Patches #1 to #16 are a rework of the Component Register setup. This
is needed to share multiple CXL capabilities (HDM and RAS) for the
same component, also there can be different components implementing
the same capability, finally RCH mode should be supported too. The
general approach to solve this is to:

   * Unify code for components and capabilities in VH and RCH modes.

   * Early setup of the Component Register base address.

   * Create and store the register mappings to later use it for mapping
     the capability I/O ranges.

Patches #17 to #23 enable CXL RCH error handling. These are needed because
RCH downstream port protocol error handling is implemented uniquely and not
currently supported. These patches address the following:

   * Discovery and mapping of RCH downstream port AER registers.

   * AER portdrv changes to support CXL RCH protocol errors. 

   * Interrupt setup specific to RCH mode: enabling RCEC internal
     errors and disabling root port interrupts.

Dan Williams (1):
  cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability

Robert Richter (16):
  cxl/acpi: Probe RCRB later during RCH downstream port creation
  cxl: Rename member @dport of struct cxl_dport to @dev
  cxl/core/regs: Add @dev to cxl_register_map
  cxl/acpi: Moving add_host_bridge_uport() around
  cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's
    port
  cxl/regs: Remove early capability checks in Component Register setup
  cxl/pci: Early setup RCH dport component registers from RCRB
  cxl/port: Store the port's Component Register mappings in struct
    cxl_port
  cxl/port: Store the downstream port's Component Register mappings in
    struct cxl_dport
  cxl/pci: Store the endpoint's Component Register mappings in struct
    cxl_dev_state
  cxl/hdm: Use stored Component Register mappings to map HDM decoder
    capability
  cxl/port: Remove Component Register base address from struct cxl_port
  cxl/port: Remove Component Register base address from struct cxl_dport
  cxl/pci: Remove Component Register base address from struct
    cxl_dev_state
  PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem
    dev handler
  PCI/AER: Unmask RCEC internal errors to enable RCH downstream port
    error handling

Terry Bowman (6):
  cxl/pci: Refactor component register discovery for reuse
  cxl/pci: Add RCH downstream port AER register discovery
  PCI/AER: Refactor cper_print_aer() for use by CXL driver module
  cxl/pci: Update CXL error logging to use RAS register address
  cxl/pci: Prepare for logging RCH downstream port protocol errors
  cxl/pci: Add RCH downstream port error logging

base-commit: a70fc4ed20a6118837b0aecbbf789074935f473b

 drivers/cxl/acpi.c            | 191 +++++++++++++++++++---------------
 drivers/cxl/core/hdm.c        |  59 +++++------
 drivers/cxl/core/pci.c        | 140 ++++++++++++++++++++++---
 drivers/cxl/core/port.c       | 157 ++++++++++++++++++++++++----
 drivers/cxl/core/region.c     |   4 +-
 drivers/cxl/core/regs.c       | 152 ++++++++++++++++++++++++---
 drivers/cxl/cxl.h             |  56 ++++++----
 drivers/cxl/cxlmem.h          |   5 +-
 drivers/cxl/mem.c             |  16 +--
 drivers/cxl/pci.c             | 109 +++++++------------
 drivers/cxl/port.c            |   5 +-
 drivers/pci/pcie/Kconfig      |  12 +++
 drivers/pci/pcie/aer.c        | 173 ++++++++++++++++++++++++++++--
 include/linux/aer.h           |   2 +-
 tools/testing/cxl/Kbuild      |   2 +-
 tools/testing/cxl/test/cxl.c  |  10 +-
 tools/testing/cxl/test/mock.c |  12 +--
 tools/testing/cxl/test/mock.h |   7 +-
 18 files changed, 824 insertions(+), 288 deletions(-)

-- 
2.34.1