[...]
On 5/11/2023 12:08 PM, Yang Weijiang wrote:
Add support for emulating read and write accesses to CET MSRs.
CET MSRs are universally "special" as they are either context switched
via dedicated VMCS fields or via XSAVES, i.e. no additional in-memory
tracking is needed, but emulated reads/writes are more expensive.
Yeah, it sounds good to me, thanks!+It may be better to merge the two if statements into one to avoid calling guest_cpuid_has(vcpu, X86_FEATURE_SHSTK) twice.
+ if (!guest_cpuid_has(vcpu, X86_FEATURE_SHSTK) &&
+ !guest_cpuid_has(vcpu, X86_FEATURE_IBT))
+ return false;
+
+ if (msr->index == MSR_IA32_PL3_SSP &&
+ !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK))
+ return false;
e.g,
if (!guest_cpuid_has(vcpu, X86_FEATURE_SHSTK) &&
(!guest_cpuid_has(vcpu, X86_FEATURE_IBT) || msr->index == MSR_IA32_PL3_SSP))
return false;
+...
+ return true;
+}
+EXPORT_SYMBOL_GPL(kvm_cet_is_msr_accessible);
+
EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);