Re: [PATCH v2 6/6] ASoC: dt-bindings: renesas,fsi: add support for multiple clocks

[Geert Uytterhoeven]

Hi Bui,

On Mon, 13 Apr 2026 at 12:07, <phucduc.bui@xxxxxxxxx> wrote:
> From: bui duc phuc <phucduc.bui@xxxxxxxxx>
>
> The FSI on r8a7740 requires the SPU bus/bridge clock to be enabled before
> accessing its registers. Without this clock, any register access leads to
> a system hang as the FSI block sits behind the SPU bus.
> Update the binding to support a flexible positional clock list to properly
> describe the hardware clock tree, including:
>   - SPU bus/bridge clock (spu) for register access.
>   - CPG DIV6 clocks (icka/b) as functional clock parents.
>   - FSI internal dividers (diva/b) for audio clock generation.
>   - External clock inputs (xcka/b) provided by the board.
>
> Signed-off-by: bui duc phuc <phucduc.bui@xxxxxxxxx>

Thanks for the update!

> Changes in v2:
>  - Rename FSI module clock to "own" to match driver.

Where does this match the driver?
Usually the functional clock is called "fck".

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds