[PATCH v5 2/9] pwm: rzg2l-gpt: Add support for gpt linking with poeg
From: Biju
Date: Mon Apr 20 2026 - 06:43:57 EST
From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
The General PWM Timer (GPT) is capable of detecting "dead time error
and short-circuits between output pins" and send Output disable
request to poeg(Port Output Enable for GPT).
Add support for linking poeg group with gpt, so that gpt can control
the output disable function by adding rzg2l_gpt_poeg_init() to parse
the renesas,poegs device tree property and establish links between POEG
groups (A–D) and GPT hardware channels (0–7). For each valid, enabled
POEG phandle entry, the driver:
- Reads the renesas,poeg-id from the POEG node and validates it against
the supported range
- Records the GPT–POEG association in a per-chip bitmap (poeg_gpt_link)
- Configures GTINTAD to route the output disable request to the correct
POEG group
- Configures GTIOR (OADF/OBDF fields) to set both output pins to
high-impedance on an output disable event
Non-enabled POEG nodes are silently skipped.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
v5:
* Updated commit description.
* Replaced return type of rzg2l_gpt_poeg_init() from void->int and
probe() checks this return value.
* Added more error checks in rzg2l_gpt_poeg_init()
V24 from [1]:
[1] https://lore.kernel.org/all/20250226144531.176819-1-biju.das.jz@xxxxxxxxxxxxxx/
---
drivers/pwm/pwm-rzg2l-gpt.c | 93 +++++++++++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index 4856af080e8e..71ae2f891fd2 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -39,6 +39,7 @@
#define RZG2L_GTCR(ch) (0x2c + RZG2L_GET_CH_OFFS(ch))
#define RZG2L_GTUDDTYC(ch) (0x30 + RZG2L_GET_CH_OFFS(ch))
#define RZG2L_GTIOR(ch) (0x34 + RZG2L_GET_CH_OFFS(ch))
+#define RZG2L_GTINTAD(ch) (0x38 + RZG2L_GET_CH_OFFS(ch))
#define RZG2L_GTBER(ch) (0x40 + RZG2L_GET_CH_OFFS(ch))
#define RZG2L_GTCNT(ch) (0x48 + RZG2L_GET_CH_OFFS(ch))
#define RZG2L_GTCCR(ch, sub_ch) (0x4c + RZG2L_GET_CH_OFFS(ch) + 4 * (sub_ch))
@@ -55,12 +56,19 @@
#define RZG2L_GTUDDTYC_UP_COUNTING (RZG2L_GTUDDTYC_UP | RZG2L_GTUDDTYC_UDF)
#define RZG2L_GTIOR_GTIOA GENMASK(4, 0)
+#define RZG2L_GTIOR_OADF GENMASK(10, 9)
#define RZG2L_GTIOR_GTIOB GENMASK(20, 16)
+#define RZG2L_GTIOR_OBDF GENMASK(26, 25)
#define RZG2L_GTIOR_GTIOx(sub_ch) ((sub_ch) ? RZG2L_GTIOR_GTIOB : RZG2L_GTIOR_GTIOA)
#define RZG2L_GTIOR_OAE BIT(8)
#define RZG2L_GTIOR_OBE BIT(24)
#define RZG2L_GTIOR_OxE(sub_ch) ((sub_ch) ? RZG2L_GTIOR_OBE : RZG2L_GTIOR_OAE)
+#define RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE BIT(9)
+#define RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE BIT(25)
+#define RZG2L_GTIOR_PIN_DISABLE_SETTING \
+ (RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE | RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE)
+
#define RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE 0x1b
#define RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH \
(RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE | RZG2L_GTIOR_OAE)
@@ -71,12 +79,17 @@
((sub_ch) ? RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH : \
RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH)
+#define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24)
+
#define RZG2L_MAX_HW_CHANNELS 8
#define RZG2L_CHANNELS_PER_IO 2
#define RZG2L_MAX_PWM_CHANNELS (RZG2L_MAX_HW_CHANNELS * RZG2L_CHANNELS_PER_IO)
#define RZG2L_MAX_SCALE_FACTOR 1024
#define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR)
+#define RZG2L_MAX_POEG_GROUPS 4
+#define RZG2L_LAST_POEG_GROUP 3
+
struct rzg2l_gpt_chip {
void __iomem *mmio;
struct mutex lock; /* lock to protect shared channel resources */
@@ -84,6 +97,7 @@ struct rzg2l_gpt_chip {
u32 period_ticks[RZG2L_MAX_HW_CHANNELS];
u32 channel_request_count[RZG2L_MAX_HW_CHANNELS];
u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS];
+ DECLARE_BITMAP(poeg_gpt_link, RZG2L_MAX_POEG_GROUPS * RZG2L_MAX_HW_CHANNELS);
};
static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *chip)
@@ -375,6 +389,81 @@ static const struct pwm_ops rzg2l_gpt_ops = {
.apply = rzg2l_gpt_apply,
};
+/*
+ * This function links a poeg group{A,B,C,D} with a gpt channel{0..7} and
+ * configure the pin for output disable.
+ */
+static int rzg2l_gpt_poeg_init(struct platform_device *pdev,
+ struct rzg2l_gpt_chip *rzg2l_gpt)
+{
+ const char *poeg_name = "renesas,poegs";
+ struct of_phandle_args of_args;
+ struct property *poegs;
+ unsigned int i;
+ u32 poeg_grp;
+ u32 bitpos;
+ int cells;
+ int ret;
+
+ poegs = of_find_property(pdev->dev.of_node, poeg_name, NULL);
+ if (!poegs)
+ return 0;
+
+ cells = of_property_count_u32_elems(pdev->dev.of_node, poeg_name);
+ if (cells < 0)
+ return cells;
+
+ if (cells & 1)
+ return -EINVAL;
+
+ cells >>= 1;
+ for (i = 0; i < cells; i++) {
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ poeg_name, 1, i,
+ &of_args);
+ if (ret)
+ return ret;
+
+ if (of_args.args[0] >= RZG2L_MAX_HW_CHANNELS) {
+ dev_err(&pdev->dev, "Invalid channel %d >= %d\n",
+ of_args.args[0], RZG2L_MAX_HW_CHANNELS);
+ goto err_of_node;
+ }
+
+ if (!of_device_is_available(of_args.np)) {
+ /* It's fine to have a phandle to a non-enabled poeg. */
+ of_node_put(of_args.np);
+ continue;
+ }
+
+ if (!of_property_read_u32(of_args.np, "renesas,poeg-id", &poeg_grp)) {
+ if (poeg_grp > RZG2L_LAST_POEG_GROUP) {
+ dev_err(&pdev->dev, "Invalid poeg group %d > %d\n",
+ poeg_grp, RZG2L_LAST_POEG_GROUP);
+ goto err_of_node;
+ }
+
+ bitpos = of_args.args[0] + poeg_grp * RZG2L_MAX_HW_CHANNELS;
+ set_bit(bitpos, rzg2l_gpt->poeg_gpt_link);
+
+ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTINTAD(of_args.args[0]),
+ RZG2L_GTINTAD_GRP_MASK, poeg_grp << 24);
+
+ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(of_args.args[0]),
+ RZG2L_GTIOR_OBDF | RZG2L_GTIOR_OADF,
+ RZG2L_GTIOR_PIN_DISABLE_SETTING);
+ }
+
+ of_node_put(of_args.np);
+ }
+
+ return 0;
+
+err_of_node:
+ of_node_put(of_args.np);
+ return -EINVAL;
+}
+
static int rzg2l_gpt_probe(struct platform_device *pdev)
{
struct rzg2l_gpt_chip *rzg2l_gpt;
@@ -426,6 +515,10 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
if (rzg2l_gpt->rate_khz * KILO != rate)
return dev_err_probe(dev, -EINVAL, "Rate is not multiple of 1000");
+ ret = rzg2l_gpt_poeg_init(pdev, rzg2l_gpt);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to link gpt with poeg\n");
+
mutex_init(&rzg2l_gpt->lock);
chip->ops = &rzg2l_gpt_ops;
--
2.43.0