[PATCH v2 1/2] dt-bindings: pinctrl: qcom,eliza-tlmm: Update function list

From: Alexander Koskovich

Date: Mon Apr 20 2026 - 12:50:01 EST


Update the function list to include the QUPs whose lanes can have more
than one GPIO option.

This allows devicetrees to override the function for say, SE6 I2C SCL
pin from 54 to 42.

Signed-off-by: Alexander Koskovich <akoskovich@xxxxx>
---
.../devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
index 282650426487..9010226bf1a0 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
@@ -86,9 +86,16 @@ $defs:
qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable,
qlink_big_request, qlink_little_enable,
qlink_little_request, qlink_wmss, qspi0, qspi_clk,
- qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
- qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,
- qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
+ qspi_cs, qup1_se0, qup1_se1, qup1_se2_l0, qup1_se2_l1,
+ qup1_se2_l2_mira, qup1_se2_l2_mirb, qup1_se2_l3_mira,
+ qup1_se2_l3_mirb, qup1_se2_l4, qup1_se2_l5, qup1_se2_l6,
+ qup1_se3, qup1_se4, qup1_se5, qup1_se6_l0, qup1_se6_l1_mira,
+ qup1_se6_l1_mirb, qup1_se6_l2, qup1_se6_l3_mira,
+ qup1_se6_l3_mirb, qup1_se7_l0_mira, qup1_se7_l0_mirb,
+ qup1_se7_l1_mira, qup1_se7_l1_mirb, qup1_se7_l2, qup1_se7_l3,
+ qup2_se0, qup2_se1, qup2_se2, qup2_se3_l0_mira,
+ qup2_se3_l0_mirb, qup2_se3_l1_mira, qup2_se3_l1_mirb,
+ qup2_se3_l2, qup2_se3_l3, qup2_se4, qup2_se5, qup2_se6,
qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2,
sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0,
tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1,

--
2.53.0