Re: [PATCH AUTOSEL 6.18] tools/power/turbostat: Fix microcode patch level output for AMD/Hygon

[Serhii Pievniev]

> Intel prescribes a sequence of WRMSR(0x8B,0) + CPUID(1) + RDMSR.
>
> This goes back to the original P6, where the upper half of the
> BBL_CR_D3 L2 cache test register was abused to report the microcode
> revision, and CPUID was abused to actually load the revision into said
> MSR. Afaik the WRMSR(0x8B,0) is still required today.

The latest Intel SDM [1] confirms that CPUID(1) is still required and
WRMSR(0x8B, 0) is recommended.

> turbostat has the prescribed CPUID(1) – by chance, a few lines earlier
> – but it lacks the prescribed WRMSR(0x8B,0).
>
> Also, note that the prescribed Intel sequence is neither required for
> AMD, nor actually works for AMD – there the MSR is read-only.

I agree that WRMSR should be added, however it is a separate issue and
should be addressed in a separate patch.

[1] https://cdrdv2-public.intel.com/916746/335592-091-sdm-vol-4.pdf