Re: [PATCH v5 19/21] clk: tegra: Add Super Gen5 Logic

From: Benson Leung
Date: Thu May 14 2015 - 15:37:31 EST

On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rklein@xxxxxxxxxx> wrote:
> From: Bill Huang <bilhuang@xxxxxxxxxx>
> Super clock divider control and clock source mux of Tegra210 has changed
> a little against prior SoCs, this patch adds Gen5 logic to address those
> differences.
> Signed-off-by: Bill Huang <bilhuang@xxxxxxxxxx>
> ---
> v2:
> - Fixed sclk divider address (0x370 -> 0x2c)
> drivers/clk/tegra/Makefile | 1 +
> drivers/clk/tegra/clk-tegra-super-gen5.c | 150 ++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk.h | 3 +
> 3 files changed, 154 insertions(+)
> create mode 100644 drivers/clk/tegra/clk-tegra-super-gen5.c

I've diffed clk-tegra-super-gen5.c and the existing
clk-tegra-super-gen4.c, and there's a lot of code duplication here.
They're the same pair of functions, with several small changes. Since
the idea behind pulling out the super clock initialization into a
common file was to reuse the same init, could we extend the super-gen4
file (rename if you have to) to support both gens instead?

Benson Leung
Software Engineer, Chrom* OS
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at
Please read the FAQ at