Re: [PATCH v6 03/19] platform/x86: intel_scu_ipc: Move legacy SCU IPC API to a separate header

[Andy Shevchenko]

On Mon, Feb 17, 2020 at 04:14:30PM +0300, Mika Westerberg wrote:
> In preparation for introducing a new API for SCU IPC, move the legacy
> API and constants to a separate header that is is subject to be removed
> eventually.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>

> Signed-off-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>
> ---
>  arch/x86/include/asm/intel_scu_ipc.h        | 56 +------------------
>  arch/x86/include/asm/intel_scu_ipc_legacy.h | 62 +++++++++++++++++++++
>  2 files changed, 63 insertions(+), 55 deletions(-)
>  create mode 100644 arch/x86/include/asm/intel_scu_ipc_legacy.h
> 
> diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h
> index 78f939782a67..a2f4694a253c 100644
> --- a/arch/x86/include/asm/intel_scu_ipc.h
> +++ b/arch/x86/include/asm/intel_scu_ipc.h
> @@ -3,22 +3,6 @@
>  #define  _ASM_X86_INTEL_SCU_IPC_H_
>  
>  #include <linux/ioport.h>
> -#include <linux/notifier.h>
> -
> -#define IPCMSG_INDIRECT_READ	0x02
> -#define IPCMSG_INDIRECT_WRITE	0x05
> -
> -#define IPCMSG_COLD_OFF		0x80	/* Only for Tangier */
> -
> -#define IPCMSG_WARM_RESET	0xF0
> -#define IPCMSG_COLD_RESET	0xF1
> -#define IPCMSG_SOFT_RESET	0xF2
> -#define IPCMSG_COLD_BOOT	0xF3
> -
> -#define IPCMSG_VRTC		0xFA	 /* Set vRTC device */
> -	/* Command id associated with message IPCMSG_VRTC */
> -	#define IPC_CMD_VRTC_SETTIME      1 /* Set time */
> -	#define IPC_CMD_VRTC_SETALARM     2 /* Set alarm */
>  
>  struct device;
>  struct intel_scu_ipc_dev;
> @@ -37,44 +21,6 @@ struct intel_scu_ipc_dev *
>  intel_scu_ipc_register(struct device *parent,
>  		       const struct intel_scu_ipc_pdata *pdata);
>  
> -/* Read single register */
> -int intel_scu_ipc_ioread8(u16 addr, u8 *data);
> -
> -/* Read a vector */
> -int intel_scu_ipc_readv(u16 *addr, u8 *data, int len);
> -
> -/* Write single register */
> -int intel_scu_ipc_iowrite8(u16 addr, u8 data);
> -
> -/* Write a vector */
> -int intel_scu_ipc_writev(u16 *addr, u8 *data, int len);
> -
> -/* Update single register based on the mask */
> -int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);
> -
> -/* Issue commands to the SCU with or without data */
> -int intel_scu_ipc_simple_command(int cmd, int sub);
> -int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
> -			  u32 *out, int outlen);
> -
> -extern struct blocking_notifier_head intel_scu_notifier;
> -
> -static inline void intel_scu_notifier_add(struct notifier_block *nb)
> -{
> -	blocking_notifier_chain_register(&intel_scu_notifier, nb);
> -}
> -
> -static inline void intel_scu_notifier_remove(struct notifier_block *nb)
> -{
> -	blocking_notifier_chain_unregister(&intel_scu_notifier, nb);
> -}
> -
> -static inline int intel_scu_notifier_post(unsigned long v, void *p)
> -{
> -	return blocking_notifier_call_chain(&intel_scu_notifier, v, p);
> -}
> -
> -#define		SCU_AVAILABLE		1
> -#define		SCU_DOWN		2
> +#include <asm/intel_scu_ipc_legacy.h>
>  
>  #endif
> diff --git a/arch/x86/include/asm/intel_scu_ipc_legacy.h b/arch/x86/include/asm/intel_scu_ipc_legacy.h
> new file mode 100644
> index 000000000000..d3a02bc07edd
> --- /dev/null
> +++ b/arch/x86/include/asm/intel_scu_ipc_legacy.h
> @@ -0,0 +1,62 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef _ASM_X86_INTEL_SCU_IPC_LEGACY_H_
> +#define _ASM_X86_INTEL_SCU_IPC_LEGACY_H_
> +
> +#include <linux/notifier.h>
> +
> +#define IPCMSG_INDIRECT_READ	0x02
> +#define IPCMSG_INDIRECT_WRITE	0x05
> +
> +#define IPCMSG_COLD_OFF		0x80	/* Only for Tangier */
> +
> +#define IPCMSG_WARM_RESET	0xF0
> +#define IPCMSG_COLD_RESET	0xF1
> +#define IPCMSG_SOFT_RESET	0xF2
> +#define IPCMSG_COLD_BOOT	0xF3
> +
> +#define IPCMSG_VRTC		0xFA	/* Set vRTC device */
> +/* Command id associated with message IPCMSG_VRTC */
> +#define IPC_CMD_VRTC_SETTIME      1	/* Set time */
> +#define IPC_CMD_VRTC_SETALARM     2	/* Set alarm */
> +
> +/* Read single register */
> +int intel_scu_ipc_ioread8(u16 addr, u8 *data);
> +
> +/* Read a vector */
> +int intel_scu_ipc_readv(u16 *addr, u8 *data, int len);
> +
> +/* Write single register */
> +int intel_scu_ipc_iowrite8(u16 addr, u8 data);
> +
> +/* Write a vector */
> +int intel_scu_ipc_writev(u16 *addr, u8 *data, int len);
> +
> +/* Update single register based on the mask */
> +int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);
> +
> +/* Issue commands to the SCU with or without data */
> +int intel_scu_ipc_simple_command(int cmd, int sub);
> +int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
> +			  u32 *out, int outlen);
> +
> +extern struct blocking_notifier_head intel_scu_notifier;
> +
> +static inline void intel_scu_notifier_add(struct notifier_block *nb)
> +{
> +	blocking_notifier_chain_register(&intel_scu_notifier, nb);
> +}
> +
> +static inline void intel_scu_notifier_remove(struct notifier_block *nb)
> +{
> +	blocking_notifier_chain_unregister(&intel_scu_notifier, nb);
> +}
> +
> +static inline int intel_scu_notifier_post(unsigned long v, void *p)
> +{
> +	return blocking_notifier_call_chain(&intel_scu_notifier, v, p);
> +}
> +
> +#define		SCU_AVAILABLE		1
> +#define		SCU_DOWN		2
> +
> +#endif
> -- 
> 2.25.0
> 

-- 
With Best Regards,
Andy Shevchenko