Re: [EXT] Re: [PATCH] bus: fsl-mc: Add ACPI support for fsl-mc
From: Lorenzo Pieralisi
Date: Mon Feb 17 2020 - 11:26:46 EST
On Mon, Feb 17, 2020 at 03:35:01PM +0000, Marc Zyngier wrote:
> On 2020-02-17 15:25, Lorenzo Pieralisi wrote:
> > On Mon, Feb 17, 2020 at 12:35:12PM +0000, Pankaj Bansal wrote:
> Hi Lorenzo,
> > > > Side note: can you explain to me please how the MSI allocation flow
> > > > and kernel data structures/drivers are modeled in DT ? I had a quick
> > > > look at:
> > > >
> > > > drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c
> > > >
> > > > and to start with, does that code imply that we create a
> > > > DOMAIN_BUS_FSL_MC_MSI on ALL DT systems with an ITS device node ?
> > >
> > > Yes. It's being done for all DT systems having ITS node.
> > This does not seem correct to me, I will let Marc comment on
> > the matter.
> Unfortunately, there isn't a very good way to avoid that ATM,
> other than defering the registration of the irqdomain until
> we know that a particular bus (for example a PCIe RC) is registered.
> I started working on that at some point, and ended up nowhere because
> no bus (PCI, FSL, or anything else) really give us the right information
> when it is actually required (when a device starts claiming interrupts).
> I *think* we could try a defer it until a bus root is found, and that
> this bus has a topological link to an ITS. probably invasive though,
> as you would need a set of "MSI providers" for each available irqchip
Yes I see, it is not trivial - I just raised the point while reading the
code to understand how the IRQ domain structures are connected in the DT
bootstrap case, I don't think that's an urgent issue to solve, just
noticed and reported it to make sure you are aware.