Re: [PATCH v4 2/2] Embedded USB Debugger (EUD) driver
From: Bryan O'Donoghue
Date: Mon Feb 17 2020 - 14:43:57 EST
On 16/02/2020 16:07, Dwivedi, Avaneesh Kumar (avani) wrote:
On 2/4/2020 8:40 AM, Bryan O'Donoghue wrote:
On 03/02/2020 19:35, Bjorn Andersson wrote:
On Thu 30 Jan 20:43 PST 2020, Avaneesh Kumar Dwivedi wrote:
Hello Bryan, Thank you very much for your review comments.
Will be replying to your comments and will be posting new patchset soon
as per review comments.
Please aim for keeping the sort order in this file (ignore QCOM_APR
which obviously is in the wrong place)
+ÂÂÂÂÂÂ tristate "QTI Embedded USB Debugger (EUD)"
+ÂÂÂÂÂÂ depends on ARCH_QCOM
If we persist with the model of EXTCON you should "select EXTCON" here.
I have asked this query with Bjorn Also against his review comments,
whether we need to persist with extcon or need to switch to usb role
switch framework, as we are notifying not only to usb controller but
also to pmic charger so in case we adopt usb role switch then how we
will notify to pmic charger to enable charging battery ? Also as i
mentioned there my dilema is it does not look very apt to model EUD hw
IP as c type connector, so please let me know your views.
I think there's a desire to model USB ports as connector child nodes of
a USB controllers as opposed to the more generic extcon so, I think the
effort should probably be made to model it up as typec.
1. Model as a typec connector
You can use usb-role-switch based on the VBUS interrupt you get
as an exmple
2. Model the registers/gpios in the PMIC interface as regulators
that your typec driver could then own.
You wouldn't have to notify outside of your typec driver then
you'd just be using the regulator API.
You can use regmap to divide up the registers between devices for that.
Can that work for you ?
+static int enable_eud(struct eud_chip *priv)
+ÂÂÂ int ret;
+ÂÂÂ /* write into CSR to enable EUD */
+ÂÂÂ writel_relaxed(BIT(0), priv->eud_reg_base + EUD_REG_CSR_EUD_EN);
+ÂÂÂ /* Enable vbus, chgr & safe mode warning interrupts */
+ÂÂÂ writel_relaxed(EUD_INT_VBUS | EUD_INT_CHGR | EUD_INT_SAFE_MODE,
+ÂÂÂÂÂÂÂÂÂÂÂ priv->eud_reg_base + EUD_REG_INT1_EN_MASK);
+ÂÂÂ /* Ensure Register Writes Complete */
So... You are writing a register in an on-chip PMIC. The PMIC is
responsible for detecting USB ID and supplying VBUS as appropriate.
You then get an interrupt to inform you of the state ?
I am writing to EUD control port so that when EUD is enable, EUD hw IP
can intercept VBUS and d+/d- signal and can reroute to PMIC or USB as
per host application command in debug mode.
Reading the dts that goes with this
+The EUD (Embedded USB Debugger) is a mini-USB hub implemented
+on chip to support the USB-based debug and trace capabilities.
Ah so, the EUD is a mux, that sits between the connector and the
controller, routing UTMI signals to an internal USB hub, which in-turn
has debug functions attached to the hub...
Can the Arm core see the hub ? I assume not ?
There are a few different modes - you should probably be clear on which
mode it is you are supporting.
Normal mode: (Bypass)
Port | EUD | Controller
Normal + debug hub mode: (Debug)
Port | EUD | Controller + HUB -> debug functions
Debug hub mode: (Control Peripheral)
Port | EUD | HUB -> debug functions
its not clear to me from the documentation or the code which mode it is
we are targeting to be supported here.
I think you should support Debug mode only here, so that the Arm core
never has to deal with the situation where the USB connector "goes away".
If we were to support Control Peripheral where the local DWC3 controller
has the signals routed away entirely, then I think we would need to look
into modelling that in device tree - and using an overlay to show the
DWC3 controller going away in Control Peripheral mode and coming back.
Also final thought since the EUD can operate in different modes, it
really should be a string that gets passed in - with the string name
aligning to the documentation "bypass", "debug" and so on, so that the
mode we are switching to is obvious to anybody who has the spec and the