Re: Re: [PATCH 1/2] tools/nolibc: riscv: Fix up load/store instructions for rv32

[Zhangjin Wu]

Hi, Willy

This is a full commit message for this patch:

When compile for rv32, we got such error:

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nolibc/sysroot/riscv/include/arch.h:190: Error: unrecognized opcode `ld a4,0(a3)'
nolibc/sysroot/riscv/include/arch.h:194: Error: unrecognized opcode `sd a3,%lo(_auxv)(a4)'
nolibc/sysroot/riscv/include/arch.h:196: Error: unrecognized opcode `sd a2,%lo(environ)(a3)'

Refer to arch/riscv/include/asm/asm.h and add REG_L/REG_S macros here to let
rv32 use its own lw/sw instructions.

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I will send a new version with the above full message for you, wait for a while, very sorry ;-)

Best Regards,
Zhangjin Wu

> Hi Zhangjin,
> 
> On Fri, May 19, 2023 at 01:02:12AM +0800, Zhangjin Wu wrote:
> > Signed-off-by: Zhangjin Wu <falcon@xxxxxxxxxxx>
> > ---
> >  tools/include/nolibc/arch-riscv.h | 14 +++++++++-----
> >  1 file changed, 9 insertions(+), 5 deletions(-)
> 
> I'm having a comment regarding this one (which for now I've queued so that
> Thomas can rebase his series), please provide a real commit message that
> explains the purpose of the change and the solutions chosen. Feel free
> to copy-paste from your cover letter if that fits, it's just that I do
> want to see some justification for a change in the commit message itself
> (i.e think about the poor person seeing a bisect stop on that one).
> 
> You can send me a paragraph or two and I'll happily copy them into my
> local copy of the rebased commit.
> 
> Thank you!
> Willy