Re: Re: [PATCH 1/2] tools/nolibc: riscv: Fix up load/store instructions for rv32

[Willy Tarreau]

On Sat, May 20, 2023 at 05:11:44PM +0800, Zhangjin Wu wrote:
> Hi, Willy
> 
> This is a full commit message for this patch:
> 
> When compile for rv32, we got such error:
> 
> ---
> 
> nolibc/sysroot/riscv/include/arch.h:190: Error: unrecognized opcode `ld a4,0(a3)'
> nolibc/sysroot/riscv/include/arch.h:194: Error: unrecognized opcode `sd a3,%lo(_auxv)(a4)'
> nolibc/sysroot/riscv/include/arch.h:196: Error: unrecognized opcode `sd a2,%lo(environ)(a3)'
> 
> Refer to arch/riscv/include/asm/asm.h and add REG_L/REG_S macros here to let
> rv32 use its own lw/sw instructions.
> 
> ---

That's fine, thank you!

> I will send a new version with the above full message for you, wait for a
> while, very sorry ;-)

Don't waste your time resending, I can perfectly take that one and
put it into the series.

Thanks!
Willy