Re: [PATCH v1] meson saradc: fix clock divider mask length

[Jonathan Cameron]

On Wed, 17 May 2023 16:47:59 +0000
Старк Георгий Николаевич <GNStark@xxxxxxxxxxxxxx> wrote:

> On 5/16/23 22:08, Martin Blumenstingl wrote:
> > Hi George,
> >
> > thank you for this patch!
> >
> > On Mon, May 15, 2023 at 11:06 PM George Stark <gnstark@xxxxxxxxxxxxxx> wrote:  
> >> From: George Stark <GNStark@xxxxxxxxxxxxxx>
> >>
> >> According to datasheets of supported meson SOCs
> >> length of ADC_CLK_DIV field is 6 bits long  
> > I have a question about this sentence which doesn't affect this patch
> > - it's only about managing expectations:
> > Which SoC are you referring to?
> > This divider is only relevant on older SoCs that predate GXBB (S905).
> > To my knowledge all SoCs from GXBB onwards place the divider in the
> > main or AO clock controller, so this bitmask is irrelevant there.  
> 
> Hello Martin
> 
> I've checked datasheets of all chips listed in meson_sar_adc_of_match array in meson_saradc.c and everywhere this field is 6 bits long. According to driver code and existing dts files this patch affects all supported chips except meson8.

On that note, do we want to add any clarifying text on the scope to the
commit message?

Jonathan

> 
> Best regards
> George
> 
> 
> >> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> >> Signed-off-by: George Stark <GNStark@xxxxxxxxxxxxxx>  
> > Since my question above doesn't affect this patch:
> > Reviewed-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx>
> >  
>