Re: [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock

[David Epping]

On Sun, May 21, 2023 at 04:12:26PM +0300, Vladimir Oltean wrote:
> Ah, no, I think the explanation is much simpler. I see the datasheet
> mentions that "RX_CLK output disable" is a sticky bit, which means it
> preserves its value across a reset.
> 
> In my case, it is the U-Boot driver which clears that setting, as part
> of configuring RGMII delays.
> https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/net/phy/mscc.c#L1553

Thanks for investigating and checking on your hardware.
Yes, my U-Boot does not support VSC850x yet, so Linux is the first
touching the registers.
For completeness: My PHY address is 0.