Re: [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock

[Vladimir Oltean]

On Sun, May 21, 2023 at 06:16:50PM +0200, David Epping wrote:
> Since we found an explanation why the current driver works in some
> setups (U-Boot), I would go with the Microchip support statement, that
> writing bit 11 to 0 is required in all modes.
> It would thus stay a separate function, called without a phy mode
> condition, and not be combined with the RGMII skew setting function.

If you still prefer to write twice in a row to the same paged register
instead of combining the changes, then fine by me, it's not a huge deal.